Method and structure for forming MOSFET with reduced parasitic capacitance
AssigneeInternational Business Machines Corporation
InventorsKangguo Cheng, Peng Xu, Chen Zhang
Life of this patent
Estimating the term…
Abstract
A method (and structure) of fabricating an MOSFET (metal-oxide-semiconductor field-effect transistor), includes, on a gate structure coated with a high-k sidewall spacer film, etching off the high-k sidewall spacer film from a top surface of the gate structure and from a portion of vertical walls of the gate structure. The etched-off high-k sidewall spacer film on the vertical walls is replaced with an ultra low-k material.
Claims14
A method of fabricating an MOSFET (metal-oxide-semiconductor field-effect transistor), said method comprising:
- on a gate structure coated with a high-k sidewall spacer film, etching off said high-k sidewall spacer film from a top surface of said gate structure and from a portion of vertical walls of said gate structure;
- depositing an ultra low-k material as a replacement for said etched-off high-k sidewall spacer film on said top surface and said vertical walls such that a thickness of said ultra low-k material is substantially constant on said top surface and on said vertical walls;
- and
- etching away, using a vertical etch, said ultra low-k material only on said top surface of said gate structure, thereby retaining said ultra low-k material on said vertical walls with said substantially constant thickness,
- wherein said gate structure controls carrier movement in an underlying channel below said gate structure and said gate structure is adjacent on each of two sides to epitaxial regions serving as source/drain functions for said MOSFET,
- wherein said etching off of said high-k sidewall spacer film comprises an etching of an exposed portion of said high-k sidewall spacer film followed by an over-etching of said high-k sidewall spacer film below a top surface of said epitaxial regions, thereby creating high-aspect-ratio divots adjacent to said gate structures, said high-aspect-ratio predetermined to permit a pinching off by a deposition of said ultra low-k material that will permit air spacers to form in said divots, said air spacers providing an ultra low-k value inside regions in said portion of vertical walls that are vacated by said over-etching.
A method of fabricating an semiconductor device, said method comprising:
- on a gate structure coated with a high-k sidewall spacer film, etching off said high-k sidewall spacer film from a portion of vertical walls of said gate structure;
- and
- depositing an ultra low-k material as a replacement for said etched-off high-k sidewall spacer film on said top surface and said vertical walls;
- and
- etching away, using a vertical etch, said ultra low-k material only on said top surface of said gate structure, thereby retaining said ultra low-k material on said vertical walls,
- wherein said gate structure controls carrier movement in an underlying channel below said gate structure and said gate structure is adjacent on each of two sides to epitaxial regions serving as source/drain functions for said semiconductor device, and
- wherein said etching off of said high-k sidewall spacer film comprises an etching of an exposed portion of said high-k sidewall spacer film followed by an over-etching of said high-k sidewall spacer film below a top surface of said epitaxial regions, thereby creating high-aspect-ratio divots between said epitaxial regions and said gate structures, said high-aspect-ratio predetermined to permit a pinching off by a deposition of said ultra low-k material that will permit air spacers to form in said divots when said ultra low-k material is deposited.
Dependencies are inferred from the claim text.