Hardmask layer for 3D NAND staircase structure in semiconductor applications
AssigneeApplied Materials, Inc.
InventorsEswaranand Venkatasubramanian, Susmit Singha Roy, Pramit Manna, Abhijit Basu Mallick
Life of this patent
Estimating the term…
Loading patent…
AssigneeApplied Materials, Inc.
InventorsEswaranand Venkatasubramanian, Susmit Singha Roy, Pramit Manna, Abhijit Basu Mallick
Estimating the term…
Embodiments of the present disclosure provide an apparatus and methods for forming a hardmask layer that may be utilized to transfer patterns or features to a film stack with accurate profiles and dimension control for manufacturing three dimensional (3D) stacked semiconductor devices. In one embodiment, a method of forming a hardmask layer on a substrate includes forming a seed layer comprising boron on a film stack disposed on a substrate by supplying a seed layer gas mixture in a processing chamber, forming a transition layer comprising born and tungsten on the seed layer by supplying a transition layer gas mixture in the processing chamber, and forming a bulk hardmask layer on the transition layer by supplying a main deposition gas mixture in the processing chamber.
A method of forming a hardmask layer on a substrate comprises:
A method of forming a hardmask layer comprising:
Dependencies are inferred from the claim text.