High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss

A multilayer structure comprising:

• a silicon wafer handle substrate comprising two major, generally parallel surfaces, one of which is a front surface of the silicon wafer handle substrate and the other of which is a back surface of the silicon wafer handle substrate, a circumferential edge joining the front and back surfaces of the silicon wafer handle substrate, and a bulk region between the front and back surfaces of the silicon wafer handle substrate, wherein the silicon wafer handle substrate has a bulk region resistivity between 2000 Ohm-cm and about 100,000 Ohm-cm;
• a charge trapping layer comprising a Group IVA nitride layer, wherein the Group IVA nitride layer comprises carbon nitride;
• a dielectric layer in contact with the Group IVA nitride layer, wherein the dielectric layer is selected from the group consisting of silicon dioxide, silicon nitride, hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide, barium oxide, and a combination thereof;
• and
• a semiconductor device layer in contact with the dielectric layer.