Method for manufacturing an SGT-including semiconductor device

A method for manufacturing an SGT-including semiconductor device, the method comprising:

• a first semiconductor pillar forming step of forming a first semiconductor pillar vertically on a substrate;
• a first impurity region forming step of forming a first impurity region in a lower portion of the first semiconductor pillar, the first impurity region containing a donor or acceptor impurity;
• a second impurity region forming step of forming a second impurity region in the first semiconductor pillar at a position above and remote from the first impurity region, the second impurity region having the same conductivity type as the first impurity region;
• a first gate insulating layer forming step of forming a first gate insulating layer so as to surround an outer periphery of the first semiconductor pillar that lies between the first impurity region and the second impurity region;
• a first gate conductor layer forming step of forming a first gate conductor layer so as to surround an outer periphery of the first gate insulating layer;
• a wiring semiconductor layer forming step of forming a wiring semiconductor layer in electrical contact with an outer peripheral side surface of the second impurity region, the outer peripheral side surface of the second impurity region extending vertically with respect to the substrate, wherein in the wiring semiconductor layer forming step, the wiring semiconductor layer is formed with a longitudinally extending side that horizontally extends in a plane passing through the outer peripheral side surface of the second impurity region;
• a first and second alloy layers forming step of forming a first alloy layer in a side surface of the wiring semiconductor layer and forming a second alloy layer in an upper surface and the side surface of the wiring semiconductor layer so that the second alloy layer is connected to the first alloy layer and separated from the second impurity region;
• a contact hole forming step of forming a contact hole on an upper surface of the second alloy layer;
• and
• a wiring metal layer forming step of forming a wiring metal layer electrically connected to the second impurity region through the contact hole,
• wherein a first SGT is formed in which when one of the first impurity region and the second impurity region serves as a source, the other serves as a drain, the first semiconductor pillar that lies between the first impurity region and the second impurity region serves as a channel, and the first gate conductor layer surrounding the outer periphery of the first gate insulating layer serves as a gate.