On-chip diagnostic circuitry monitoring multiple cycles of signal samples

An integrated circuit comprising:

• a plurality of internal nets, each carrying a respective one of a plurality of signals;
• and
• diagnostic circuitry coupled with at least one of the plurality of internal nets, the diagnostic circuitry comprising:
• slew rate diagnostic circuitry configured to generate, based on a selected signal of the plurality of signals, a slew rate signal comprising a pulse having a pulse width, the pulse width indicating a slew rate of the selected signal, wherein the slew rate diagnostic circuitry includes:
• a fast-switching circuitry configured to receive the selected signal and produce a first output signal indicating transitions in the selected signal in response to the selected signal exceeding a first voltage threshold;
• slow-switching circuitry configured to receive the selected signal and produce a second output signal indicating the transitions in the selected signal with a delay compared to the first output signal in response to the selected signal exceeding a second voltage threshold greater than the first voltage threshold;
• and
• an exclusive-OR (XOR) gate configured to receive the first and second output signals and to generate the slew rate signal;
• a memory comprising a plurality of data lines and a plurality of address lines;
• and
• a plurality of delay elements, each delay element of the plurality of delay elements connected between consecutive data lines of the plurality of data lines,
• wherein the diagnostic circuitry is configured to write, upon receiving a trigger signal, values on the plurality of data lines to the plurality of address lines, thereby acquiring a plurality of samples of the slew rate signal corresponding to a plurality of transitions of the selected signal.

An integrated circuit comprising:

• a plurality of internal nets each carrying a respective one of a plurality of signals;
• a fast-switching circuit configured to receive a selected signal of the plurality of signals and to produce a first output signal in response to the selected signal transitioning above a first voltage threshold as a first transition indicator;
• a slow-switching circuit configured to receive the selected signal and to produce a second output signal in response to the selected signal above a second voltage threshold that is higher than first voltage threshold as a second transition indicator;
• a pulse generating circuit configured to generate a pulse based on the first and second transition indicators;
• and
• diagnostic circuitry comprising a memory having a plurality of data lines and a plurality of address lines, wherein the diagnostic circuitry is configured to acquire a plurality of samples of the generated pulse in the memory.