Semiconductor circuit

A method for testing a plurality of memories, including a first memory and a second memory, each including an array of memory cells, the method comprising:

• writing a test pattern including an address and data to the first memory;
• reading data output from the first memory, and writing the data output from the first memory into the second memory;
• reading data output from the second memory, and capturing the data output from the second memory;
• comparing the captured data to expected data to determine whether there is a mismatch;
• and
• upon detecting a mismatch, generating a flag indicating that either the first or the second memory has a defective memory cell.

A circuit for testing a plurality of memories, including a first memory and a second memory each including an array of memory cells, comprising:

• a built-in self test (BIST) circuit operable during a test mode to generate control signals, address signals, pattern data and expected data for testing the arrays of memory cells of the first and second memories;
• a first plurality of selectors that receives address signals, the pattern data and control signals from the BIST circuit, and provides the received address signals, pattern data and the control signals to the first memory;
• an address register that receives and latches the address signals from the BIST circuit;
• a second plurality of selectors that receives the latched address signals from the address register and control signals from BIST circuit and provides the latched address signals and control signals to the second memory;
• a third plurality of selectors that connects data outputs of the first memory to data inputs of the second memory;
• a capture register that captures data output from the second memory;
• and
• a comparison circuit that compares the expected data with data in the capture register and provides a flag indicating whether a memory cell in either the first or second memory is defective.