Memory control circuit and memory test method

A memory control circuit, coupled to a multi-channel memory, the multi-channel memory comprises a plurality of channel memories, the memory control circuit comprising:

• a plurality of channel controllers, coupled to a respective one of a plurality of channel memories of the multi-channel memory;
• and
• a built-in self-test (BIST) circuit, coupled to the channel controllers, the BIST circuit including a BIST controller and a plurality of command index registers, the BIST controller being coupled to the channel controllers, the command index registers being coupled to the BIST controller, the command index registers storing respective command indexes of the channel controllers, wherein
• the BIST controller receives inform from at least two of the channel controllers which indicates that the informing at least two channel controllers already complete respective current test commands;
• when the BIST controller arbitrates, the BIST controller selects at least one channel controller from the informing at least two channel controllers, and based on the respective command index(es) of the selected at least one channel controller, the BIST controller sends respective next test command(s) to the selected at least one channel controller,
• the BIST controller determines whether the BIST controller is capable of concurrently sending the respective next test command(s) to the informing at least two channel controllers;
• if the BIST controller determines that the BIST controller is capable of concurrently sending the respective next test command(s) to the informing at least two channel controllers, based on the respective command indexes of the informing at least two channel controllers, the BIST controller sends the respective next test command(s) to the informing at least two channel controllers and updates the respective command indexes of the informing at least two channel controllers;
• and
• if the BIST controller determines that the BIST controller is not capable of concurrently sending the respective next test command(s) to the informing at least two channel controllers, the BIST controller selects at least m channel controller(s) among the informing at least two channel controllers, m being a maximum type number of the test commands that the BIST controller is allowed to concurrently send, and based on the respective command indexes of the selected at least m channel controller(s), the BIST controller sends the respective next test command(s) to the selected at least m channel controller(s) and updates the respective command index(es) of the selected at least m channel controller(s).