Data processing

A data processing apparatus comprising:

• at least one memory means for storing data;
• processing means to access data in the at least one memory means, the at least one memory means comprising a cache memory means;
• memory built-in self-test (MBIST) means having an interface means for accessing the at least one memory and being configured to perform a test procedure for testing at least one target memory location of the at least one memory, the test procedure comprising at least writing test data to the target memory location;
• and
• diagnostic means for executing a diagnostic procedure to generate diagnostic data in response to processing operations carried out by the processing means;
• cache controller means for controlling the storage of data to, and the retrieval of data from, the cache memory means;
• and
• control means for reserving a memory region comprising at least a portion of the at least one memory means, to store the diagnostic data generated by the diagnostic circuitry executing the diagnostic procedure;
• wherein:
• the MBIST means is configured to control writing of the diagnostic data generated by the diagnostic means to memory locations in a temporarily reserved memory region comprising at least a portion of the at least one memory means;
• the cache controller means is operable to allocate portions of the cache memory means for temporary storage of data corresponding to addresses in a higher level memory;
• and
• the control means is operable to reserve a memory region of the cache memory means by indicating to the cache controller means that the temporarily reserved memory region is unavailable for allocation by the cache controller means.

A data processing method comprising:

• providing memory built-in self-test (MBIST) circuitry having an interface to a cache memory to execute a test procedure for testing at least one target memory location of the cache memory, the MBIST test procedure comprising at least writing test data to the target memory location;
• controlling, using a cache controller, the storage of data to, and the retrieval of data from, the cache memory;
• the cache controller allocating portions of the cache memory for temporary storage of data corresponding to addresses in a higher level memory;
• temporarily reserving a memory region comprising at least a portion of the at least one memory;
• executing a diagnostic procedure to generate diagnostic data in response to processing operations;
• and
• the MBIST circuitry controlling writing of the diagnostic data generated by the executing step to memory locations in a memory region reserved by the temporarily reserving step;
• the reserving step comprising indicating to the cache controller that the memory region reserved by the temporarily reserving step is unavailable for allocation by the cache controller.