Shift register unit and driving unit thereof, gate electrode driving circuit and display apparatus

A driving method of a shift register unit, the shift register unit comprising an input circuit, an output circuit, a control circuit, a reset circuit and a switch circuit, and the method comprising:

• an input stage during which an input signal output by an input signal end has a first electric potential, a second clock signal output by a second clock signal end has the first electric potential, the input circuit charges a first node, the control circuit inputs a first power source signal from a first power source signal end to a third node and inputs a second power source signal from a second power source signal end to a second node, the switch circuit controls the second and third nodes to be disconnected under the control of the input signal and the second power source signal, wherein the first power source signal has a first electric potential and the second power source signal has a second electric potential;
• an output stage during which a first clock signal output by a first clock signal end has the first electric potential, the first node maintains the first electric potential, the output circuit inputs the first clock signal to the output end under the control of the first node, and the switch circuit controls the second and third nodes to be connected under the control of the first clock signal and the first power source signal;
• and
• a reset stage during which the second clock signal has the first electric potential, the control circuit inputs the first power source signal to the third node, the switch circuit controls the second and third nodes to maintain their connected states so that the electric potential of the third node is written into the second node, and the reset circuit inputs the second power source signal to the first node and the output end respectively under the control of the second node.

A gate electrode driving circuit, comprising:

• at least two cascading shift register units, each of which comprising:
• an input circuit, an output circuit, a control circuit, a reset circuit, and a switch circuit;
• wherein
• the input circuit is connected to an input signal end and a first node respectively, and is configured to control the electric potential of the first node under the control of an input signal from the input signal end;
• the output circuit is respectively connected to a first clock signal end, the first node, and an output end, and is configured to input a first clock signal from the first clock signal end to the output end under the control of the first node;
• the control circuit is connected to a second clock signal end, a first power source signal end, a second power source signal end, the first node, a second node and a third node respectively, and is configured to input a second power source signal from the second power source signal end to the second node under the control of the first node and input a first power source signal from the first power source signal end to the third node under the control of a second clock signal from the second clock signal end, wherein the first power source signal has a first electric potential and the second power source signal has a second electric potential;
• the reset circuit is connected to the second node, the first node, the output end and the second power source signal end respectively, and is configured to input the second power source signal to the first node and the output end under the control of the second node;
• the switch circuit is connected to the input signal end, the first clock signal end, the first power source signal end, the second power source signal end, the second node and the third node respectively, and is configured to control the second and third nodes to be disconnected through the second power source signal when the input signal has the first electric potential, and control the second and third nodes to be connected through the first power source signal when the first clock signal has the first electric potential.