Method and apparatus for reading RRAM cell

A memory circuit, comprising:

• a memory array;
• a word-line decoder configured to apply a first non-zero read voltage to a word-line coupled to a selected memory cell and to a plurality of unselected memory cells within the memory array;
• a bit-line decoder configured to apply a second non-zero read voltage to a first bit-line coupled to the selected memory cell during a read operation;
• and
• a bias element configured to apply a first non-zero bias voltage to additional bit-lines coupled to the plurality of unselected memory cells concurrent to the bit-line decoder applying the second non-zero read voltage to the first bit-line during the read operation.

A method of operating a resistive random access memory (RRAM) array, comprising:

• performing a read operation on a selected RRAM device, by:
• activating a word-line coupled to the selected RRAM device and a plurality of unselected RRAM devices by applying a word-line voltage to the word-line;
• applying a first non-zero bit-line voltage to a first bit-line coupled to the selected RRAM device;
• and
• applying a first non-zero bias voltage to a plurality of additional bit-lines or applying a second non-zero bias voltage to a plurality of additional select-lines concurrent to applying the first non-zero bit-line voltage to the first bit-line, wherein the plurality of additional bit-lines and the plurality of additional select-lines are coupled to the plurality of unselected RRAM devices.