Semiconductor memory device with assymetric precharge

A semiconductor memory device comprising:

• a memory cell connected between a first bit line and a second bit line;
• and
• a bit line voltage control circuit connected between the first bit line and the second bit line, the bit line voltage control circuit configured to apply a first precharge voltage to the first bit line and a second precharge voltage to the second bit line,
• wherein the bit line voltage control circuit comprises a first transistor, a second transistor, a first switch, and a second switch,
• wherein a first gate node of the first transistor is connected to the second bit line,
• wherein the first gate node and a first drain node of the first transistor are connected to the first switch,
• wherein a second gate node of the second transistor is connected to the first bit line,
• wherein the second gate node and a second drain node of the second transistor are connected to the second switch,
• wherein a first source node of the first transistor and a second source node of the second transistor are directly connected to a voltage source to receive a supply voltage for precharging the first bit line and the second bit line.

A semiconductor memory device comprising:

• a memory cell;
• a sensing circuit configured to sense data stored in the memory cell;
• and
• a bit line voltage control circuit connected to the memory cell via a first bit line and a second bit line,
• wherein the bit line voltage control circuit is configured to apply a first precharge voltage to the first bit line and apply a second precharge voltage to the second bit line during a precharge period, the first precharge voltage being different from the second precharge voltage,
• wherein a first voltage at the first bit line decreases and a second voltage at the second bit line increases during a sensing period, and
• wherein the bit line voltage control circuit is configured to precharge the first bit line to the first precharge voltage and the second bit line to the second precharge voltage during a precharge operation, and to amplify a difference value between the first precharge voltage and the second precharge voltage during a read operation subsequent to the precharge operation,
• wherein the bit line voltage control circuit comprises a first transistor configured to precharge the second bit line to the second voltage and a second transistor configured to precharge the first bit line to the first voltage, and
• wherein a first source node of the first transistor and a second source node of the second transistor are directly connected to a voltage source to receive the supply voltage for precharging the first bit line and the second bit line.