Semiconductor device with a plurality of surrounding gate transistors

A semiconductor device forming a decoder circuit, comprising:

• a plurality of rows each row including a NAND decoder connected to an inverter, each NAND decoder including a plurality of transistors arranged on a substrate in M rows and N columns, each of the plurality of transistors having a source, a drain, and a gate in layers arranged in a direction perpendicular to the substrate;
• each of the plurality of transistors including:
• a silicon pillar, an insulator surrounding a side surface of the silicon pillar, a gate surrounding the insulator, a source region arranged on a top or on a bottom of the silicon pillar;
• and
• a drain region on the top or on the bottom of the silicon pillar, on a side of the silicon pillar opposite from the source region;
• each NAND decoder including i P-channel MOS transistors, and i N-channel MOS transistors, where i=3 or 4, and wherein in the i P-channel MOS transistors and the i N-channel MOS transistors, a k-th P-channel MOS transistor, where k=1 to n 4, and a k-th N-channel MOS transistor constitute a pair, and the gate of the k-th P-channel MOS transistor and the gate of the k-th N-channel MOS transistor are connected to each other;
• the drain regions of the i P-channel MOS transistors and the drain region of a first N-channel MOS transistor are arranged on a side of the silicon pillars closer to the substrate, and the drain regions of the i P-channel MOS transistors and the drain region of the first N-channel MOS transistor are connected to one another via a silicide region;
• the source region of an s-th N-channel MOS transistor, where s=1 to i−1, and the drain region of an s+1-th N-channel MOS transistor are connected to each other via a connection including a silicide region;
• the source regions of the i P-channel MOS transistors are each connected to a supply voltage line, and the source region of an i-th N-channel MOS transistor is connected to a reference voltage line;
• the gates of k pairs of MOS transistors, the gates of each pair of MOS transistors being connected to each other, are connected to input signal lines, where the gate of a first N-channel MOS transistor is connected to a same signal line as a first P-channel MOS transistor and gates of a second and a third P-channel transistor are each connected to a different signal line than the gate of the first N-channel MOS transistor;
• and
• the supply voltage line, the reference voltage line, and the input signal lines extend in an identical direction,
• wherein the i P-channel MOS transistors are arranged in M rows and one column, the i N-channel MOS transistors are arranged in M rows and one column, and the supply voltage line, the reference voltage line, and the input signal lines extend in a direction perpendicular to a row direction.

A semiconductor device forming a decoder circuit, comprising:

• a plurality of rows each row including a NAND decoder connected to an inverter, each NAND decoder including a plurality of transistors on a substrate in M rows and N columns, each of the plurality of transistors having a source, a drain, and a gate in layers in a direction perpendicular to the substrate;
• each of the plurality of transistors including:
• a silicon pillar, an insulator surrounding a side surface of the silicon pillar, a gate surrounding the insulator, a source region arranged on a top or on a bottom of the silicon pillar, and
• a drain region arranged on the top or on the bottom of the silicon pillar, on a side of the silicon pillar opposite to the source region:
• each NAND decoder including i P-channel MOS transistors, and i N-channel MOS transistors, where i=3 or 4, and wherein in the i P-channel MOS transistors and the i N-channel MOS transistors, a k-th P-channel MOS transistor, where k=1 to, and a k-th N-channel MOS transistor constitute a pair, and the gate of the k-th P-channel MOS transistor and the gate of the k-th N-channel MOS transistor are connected to each other,
• the source regions of the i P-channel MOS transistors and the source region of a first N-channel MOS transistor are arranged on a side of the silicon pillars closer to the substrate, and the drain regions of the i P-channel MOS transistors and the drain region of the first N-channel MOS transistor are connected to one another via contacts,
• the source region of an s-th N-channel MOS transistor, where s=1 to i−1, and the drain region of an s+1-th N-channel MOS transistor are connected to each other,
• the source regions of the i P-channel MOS transistors are each connected to a supply voltage line, and the source region of an i-th N-channel MOS transistor is connected to a reference voltage line, the gates of k pairs of MOS transistors,
• the gates of each pair of MOS transistors being connected to each other, are connected to input signal lines, and the supply voltage line, the reference voltage line, and the input signal lines extend in an identical direction, where the gate of a first N-channel MOS transistor is connected to a same signal line as a first P-channel MOS transistor and gates of a second and a third P-channel transistor are each connected to a different signal line than the gate of the first N-channel MOS transistor,
• and the supply voltage line, the reference voltage line, and the input signal lines extend in an identical direction,
• wherein the source regions of P-channel MOS transistors adjacent to each other in the decoder circuit are connected in common via a silicide region.

A semiconductor device forming a decoder circuit, comprising:

• a plurality of rows each row including a NAND decoder connected to an inverter, each NAND decorder including a plurality of transistors arranged on a substrate in M rows and N columns, each of the plurality of transistors having a source, a drain, and a gate in layers in a direction perpendicular to the substrate;
• each of the plurality of transistors including:
• a silicon pillar, an insulator surrounding a side surface of the silicon pillar, a gate surrounding the insulator, a source region arranged on a top or on a bottom of the silicon pillar, and a drain region arranged on the top or on the bottom of the silicon pillar, on a side of the silicon pillar opposite to the source region:
• each NAND decoder including i P-channel MOS transistors, and i N-channel MOS transistors, where i=3 or 4, and wherein in the i P-channel MOS transistors and the i N-channel MOS transistors, a k-th P-channel MOS transistor, where k=1 to, and a k-th N-channel MOS transistor constitute a pair, and the gate of the k-th P-channel MOS transistor and the gate of the k-th N-channel MOS transistor are connected to each other,
• the source regions of the i P-channel MOS transistors and the source region of a first N-channel MOS transistor are arranged on a side of the silicon pillars closer to the substrate, and the drain regions of the i P-channel MOS transistors and the drain region of the first N-channel MOS transistor are connected to one another via contacts,
• the source region of an s-th N-channel MOS transistor, where s=1 to n−1, and the drain region of an s+1-th N-channel MOS transistor are connected to each other,
• the source regions of the i P-channel MOS transistors are each connected to a supply voltage line, and the source region of an n-th N-channel MOS transistor is connected to a reference voltage line,
• the gates of k pairs of MOS transistors, the gates of each pair of MOS transistors being connected to each other, are connected to input signal lines, where the gate of a first N-channel MOS transistor is connected to a same signal line as a first P-channel MOS transistor and gates of a second and a third P-channel transistor are each connected to a different signal line than the gate of the k first N-channel MOS transistor, and
• the supply voltage line, the reference voltage line, and the input signal lines extend in an identical direction,
• wherein the i P-channel MOS transistors are arranged in M rows and one column, the i N-channel MOS transistors are arranged in M rows and one column, and the supply voltage line, the reference voltage line, and the input signal lines extend in a direction perpendicular to a row direction,
• wherein the source regions of P-channel MOS transistors adjacent to each other in the decoder circuit are connected in common via a silicide region.

A semiconductor device forming a static memory including a plurality of transistors arranged on a substrate, each of the plurality of transistors having a source, a drain, and a gate in layers in a direction perpendicular to the substrate, the static memory comprising:

• a plurality of static memory cells each including at least six MOS transistors arranged on an insulating film formed on the substrate and arranged in a matrix;
• a plurality of row address circuits each specifying one row-line of the static memory cells;
• and
• a plurality of row decoder circuits each including a plurality of MOS transistors and each selecting one row of the static memory cells in accordance with signals from the row address circuits;
• each of the six MOS transistors that constitute each of the static memory cells, and each of the plurality of MOS transistors that constitute each of the row decoder circuits including:
• a silicon pillar, an insulator surrounding a side surface of the silicon pillar, a gate surrounding the insulator, a source region arranged on a top or on a bottom of the silicon pillar, and a drain region arranged on the top or on the bottom of the silicon pillar, on a side of the silicon pillar opposite from source region, the six MOS transistors included in each of the static memory cells being arranged in two rows and three columns, each of the row decoder circuits including at least n P-channel MOS transistors arranged in one row and N columns, i N-channel MOS transistors arranged in one row and N columns, and an inverter,
• wherein, in the i P-channel MOS transistors and the i N-channel MOS transistors, a P-channel MOS transistor in a k-th column, where k=1 to n and n=2 to 4, arranged in one row and an N-channel MOS transistor in the k-th column arranged in one row constitute a pair, and the gate of the P-channel MOS transistor in the k-th column and the gate of the N-channel MOS transistor in the k-th column are connected to each other, the drain regions of the i P-channel MOS transistors and the drain region of an N-channel MOS transistor in a first column are arranged on a side of the silicon pillars closer to the substrate, and the drain regions of the i P-channel MOS transistors and the drain region of the N-channel MOS transistor in the first column are connected to one another via a silicide region, the source region of an N-channel MOS transistor in an s-th column, where s=1 to n−1, and the drain region of an N-channel MOS transistor in an s+1-th column are connected to each other, the source regions of the i P-channel MOS transistors are each connected to a supply voltage line that extends in a direction perpendicular to the row, and the source region of an N-channel MOS transistor in an N-th column is connected to a reference voltage line that extends in the direction perpendicular to the row, input signal lines that are connected to the gates of k pairs of MOS transistors, the gates of each pair of MOS transistors being connected to each other, are constituted by lines that extend in the direction perpendicular to the row, and the drain regions of the i P-channel MOS transistors and the drain region of the N-channel MOS transistor in the first column are connected to an input gate of the inverter, and output of the inverter is connected to a row selection line of the static memory cells.

A semiconductor device forming a static memory including a plurality of transistors arranged on a substrate, each of the plurality of transistors having a source, a drain, and a gate arranged in layers in a direction perpendicular to the substrate, the static memory comprising:

• a plurality of static memory cells each including at least six MOS transistors arranged on an insulating film formed on the substrate and arranged in a matrix;
• a plurality of row address circuits each specifying one row-line of the static memory cells;
• and
• a plurality of row decoder circuits each including a plurality of MOS transistors and each selecting one row of the static memory cells in accordance with signals from the row address circuits, each of the six MOS transistors that constitute each of the static memory cells, and each of the plurality of MOS transistors that constitute each of the row decoder circuits including a silicon pillar, an insulator surrounding a side surface of the silicon pillar, a gate surrounding the insulator, a source region arranged on a top or on a bottom of the silicon pillar, and a drain region arranged on the top or on the bottom of the silicon pillar, on a side of the silicon pillar opposite from the source region, the six MOS transistors included in each of the static memory cells being arranged in two rows and three columns, each of the row decoder circuits including at least n P-channel MOS transistors arranged in one row and N columns, n N-channel MOS transistors arranged in one row and N columns, and an inverter,
• wherein, in the i P-channel MOS transistors and the i N-channel MOS transistors, a P-channel MOS transistor in a k-th column, where k=1 to n and n=2 to 4, arranged in one row and an N-channel MOS transistor in the k-th column arranged in one row constitute a pair, and the gate of the P-channel MOS transistor in the k-th column and the gate of the N-channel MOS transistor in the k-th column are connected to each other, the source regions of the i P-channel MOS transistors and the source region of an N-channel MOS transistor in a first column are arranged on a side of the silicon pillars closer to the substrate, and the drain regions of the i P-channel MOS transistors and the drain region of the N-channel MOS transistor in the first column are connected to one another via contacts, the source region of an N-channel MOS transistor in an s-th column, where s=1 to n−1, and the drain region of an N-channel MOS transistor in an s+1-th column are connected to each other, the source regions of the i P-channel MOS transistors are each connected to a supply voltage line that extends in a direction perpendicular to the row, and the source region of an N-channel MOS transistor in an N-th column is connected to a reference voltage line that extends in the direction perpendicular to the row, input signal lines that are connected to the gates of n pairs of MOS transistors, the gates of each pair of MOS transistors being connected to each other, are constituted by lines that extend in the direction perpendicular to the row, and the drain regions of the i P-channel MOS transistors and the drain region of the N-channel MOS transistor in the first column are connected to an input gate of the inverter, and output of the inverter is connected to a row selection line of the static memory cells.