US 10,311,944 B2 · SRAM read multiplexer including replica transistors

Abstract

A first transistor has a first conduction terminal coupled to a second bit line, a second conduction terminal coupled to a bit line node, and a control terminal biased by a second control signal. A second transistor has a first conduction terminal coupled to a second complementary bit line, a second conduction terminal coupled to a complementary bit line node, and a control terminal biased by the second control signal. A first replica transistor has a first conduction terminal coupled to the second bit line, a second conduction terminal coupled to the complementary bit line node, and a control terminal biased such that the first replica transistor is off. A second replica transistor has a first conduction terminal coupled to the second complementary bit line, a second conduction terminal coupled to the bit line node, and a control terminal biased such that the second replica transistor is off.

Claims21

Dependent claims

An electronic device, comprising:

a sense amplifier having first and second inputs;
a first column coupled to the first and second inputs of the sense amplifier, the first column comprising:
a first memory cell coupled to a first bitline;
a first transistor coupled between the first bitline and the first input of the sense amplifier;
and
a first replica transistor coupled between the first bitline and the second input of the sense amplifier, wherein the first replica transistor is a replica of the first transistor;
and
a second column coupled to the first and second inputs of the sense amplifier.

5 more elements

An electronic device, comprising:

a sense amplifier having first and second inputs;
and
a first column comprising:
a first memory cell coupled to a first bitline and a first complementary bitline;
a first read transistor coupled between the first complementary bitline and the second input of the sense amplifier;
a first replica transistor coupled between the first complementary bitline and the first input of the sense amplifier, wherein the first replica transistor is a replica of the first read transistor;
a second read transistor coupled between the first bitline and the first input of the sense amplifier;
and
a second replica transistor coupled between the first bitline and the second input of the sense amplifier, wherein the second replica transistor is a replica of the second read transistor;
wherein the first and second replica transistors have control terminals coupled to a fixed voltage node.

7 more elements

An electronic device, comprising:

a sense amplifier having a non-inverting input and an inverting input;
and
a first column comprising:
a first memory cell coupled to a first bitline and a first complementary bitline;
a first read PMOS transistor having a source coupled to the first complementary bitline, a drain coupled to the inverting input of the sense amplifier, and a gate coupled to a first control signal node;
and
a first replica transistor having a source coupled to the first complementary bitline, a drain coupled to the non-inverting input of the sense amplifier, and a gate coupled to a power supply node, wherein the first replica transistor is a replica of the first read PMOS transistor;
a second read PMOS transistor having a source coupled to the first bitline, a drain coupled to the non-inverting input of the sense amplifier, and a gate coupled to the first control signal node;
and
a second replica transistor having a source coupled to the first bitline, a drain coupled to the inverting input of the sense amplifier, and a gate coupled to the power supply node, wherein the second replica transistor is a replica of the second read PMOS transistor.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application

16/025,647Filed 2 Jul 2018 · continuation

Priority

26 Jul 2017

Published

US 2019/0035454 A131 Jan 2019

Granted

4 Jun 2019

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

G11C 11/417
Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction: for memory cells of the field-effect type
G11C 11/419
For memory cells of the field-effect type: read-write [R-W] circuits
G11C 5/14
Details of stores covered by group G11C11/00: power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or…
G11C 7/227
Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management: timing of memory operations based on dummy…

SRAM read multiplexer including replica transistors

Life of this patent

SRAM read multiplexer including replica transistors

Life of this patent

Abstract

Claims21