Back to results
US 10,311,928 B2Granted
Semiconductor devices including reversible and one-time programmable magnetic tunnel junctions
AssigneeSamsung Electronics Co., Ltd.
InventorsBoyoung Seo, Yongkyu Lee, Gwanhyeob Koh, Choong Jae Lee
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a memory cell array, which further includes an array of first magnetic memory cells and an array of second magnetic memory cells. Each of the first magnetic memory cells includes a first magnetic tunnel junction structure having a reversible resistance state, and each of the second magnetic memory cells includes a second magnetic tunnel junction structure having a one-time programmable (OTP) resistance state.
Claims19
A semiconductor device, comprising:
- a plurality of word lines;
- a plurality of bit lines crossing the plurality of word lines, the plurality of bit lines including first bit lines and second bit lines, the second bit lines spaced apart from the first bit lines in a direction of extension of the plurality of word lines;
- a plurality of first memory cells connected between the plurality of word lines and the first bit lines, each of the plurality of first memory cells including a first memory element and a first selection element, the first memory element and the first selection element connected to each other;
- and
- a plurality of second memory cells connected between the plurality of word lines and the second bit lines, each of the plurality of second memory cells including a second memory element and a second selection element, the second memory element and the second selection element connected to each other,
- wherein the first memory element includes a first magnetic tunnel junction, and the second memory element includes a second magnetic tunnel junction, each of the first magnetic tunnel junction and the second magnetic tunnel junction including a pinned layer, a free layer, and a tunnel barrier layer between the pinned layer and the free layer,
- wherein the tunnel barrier layers of a first portion of the second magnetic tunnel junctions have an irreversible resistance state,
- wherein the first magnetic tunnel junction has a rewritable structure, and is configured to have one of (i) a first resistance corresponding to first data, and (ii) a second resistance corresponding to second data,
- wherein at least one second magnetic tunnel junction among the first portion of the second magnetic tunnel junctions has a third resistance corresponding to the first data, the at least one second magnetic tunnel junction having been programmed through a first one-time programming operation, and
- wherein the first resistance, the second resistance and the third resistance are different from each other.
7 more elements
A semiconductor device, comprising:
- a memory cell array including an array of reprogrammable cells and an array of one-time programmable (OTP) cells;
- a first peripheral circuit electrically connected to the array of reprogrammable cells through first bit lines;
- and
- a second peripheral circuit electrically connected to the array of OTP cells through second bit lines;
- wherein
- the array of reprogrammable cells includes a plurality of first memory cells, each of the plurality of first memory cells including a first magnetic tunnel junction and a first selection transistor, the first magnetic tunnel junction and the first selection transistor connected to each other,
- the array of OTP cells includes a plurality of second memory cells, each of the plurality of second memory cells including a second magnetic tunnel junction and a second selection transistor, the second magnetic tunnel junction and the second selection transistor connected to each other,
- a first portion of the second magnetic tunnel junctions have an irreversible resistance state,
- the first peripheral circuit includes at least one first peripheral transistor,
- the second peripheral circuit includes at least one second peripheral transistor, and
- the at least one second peripheral transistor is configured to operate in response to a voltage higher than the at least one first peripheral transistor.
8 more elements
A semiconductor device comprising:
- a memory cell array including an array of first magnetic memory cells and an array of second magnetic memory cells, each first magnetic memory cell in the array of first magnetic memory cells including a first magnetic tunnel junction structure having a rewritable structure, and each second magnetic memory cell in the array of second magnetic memory cells including a second magnetic tunnel junction structure having a one-time programmable (OTP) resistance state;
- wherein
- the first magnetic tunnel junction structure has one of (i) a first resistance corresponding to first data, and (ii) a second resistance corresponding to second data,
- the second magnetic tunnel junction structure has a third resistance corresponding to the first data, the second magnetic tunnel junction structure having been programmed through a one-time programming operation, and
- the first resistance, the second resistance and the third resistance are different from each other.
2 more elements
Dependencies are inferred from the claim text.