A complimentary metal-oxide-semiconductor (CMOS) gate driver on array (GOA) circuit, comprising:
- a plurality of stages of GOA units, wherein the odd-numbered stages of GOA units being cascaded and the even-numbered stages of GOA units being cascaded;
- each GOA unit comprising:
- a forward-and-backward scan control module, a control input module, a reset module, a latch module, a signal processing module, and an output buffer module;
- for positive numbers M and N, other than the GOA units in the first stage, the second stage, the second last stage and the last stage, in each N-th GOA unit:
- the forward-and-backward scan control module being connected to receive a voltage signal of a first node of the (N−2)-th GOA unit, a voltage signal of a first node of the (N+2)-th GOA unit, a forward scan signal and a backward scan signal, for controlling the GOA circuit to perform forward scan or backward scan according to the voltage change of the forward scan signal and the backward scan signal;
- the control input module being connected to the forward-and-backward control module and receiving an M-th clock signal and an M-th inverse clock signal, for inverting the voltage signal of the first node of the (N−2)-th GOA unit or the first node of the (N+2)-th GOA unit transmitted from the forward-and-backward control module according to the M-th clock signal and the M-th inverse clock signal, and outputting to a second node;
- the reset module being connected to receive a reset signal and a constant high voltage signal, and connected to the second node for clearing the voltage signal of the first node according to the reset signal;
- the latch module being connected to receive the M-th clock signal and the M-th inverse clock signal, and connected to the first node and the second node, for inverting a voltage signal of the second node and outputting to the first node, and latching the voltage signal of the first node according to the M-th clock signal and the M-th inverse clock signal to maintain the voltage signals of the first node and the second node having opposite phases;
- the signal processing module comprising:
- a first TFT and a second TFT;
- the first TFT having a gate connected to receive a first control signal, a source connected to an output node that is one of the first node and the second node and a drain connected to a third node;
- the second TFT having a gate and a source connected to receive a second control signal, and a drain connected to the third node;
- the first control signal and the second control signal having opposite phases, the first control signal and the second control signal controlling the first TFT and the second TFT to turn on alternatingly input a voltage signal of the output node or a second control signal to the third node, wherein the drain of the first TFT and the drain of the second TFT are connected to each other;
- and the source of the first TFT is connected to the output node that receives a first signal therefrom and the source of the second TFT receives the second control signal as a second signal that is different from the first signal so that the sources of the first and second TFTs are arranged to receive different signals and the signal processing module is operable to selectively and alternatively transmit the first signal and the second signal to the third node;
- the output buffer module being connected to the third node, for inverting a voltage signal of the third node a plurality of times before outputting as a gate scan driving signal.