Gate driving circuit and display device including the same

A display device comprising:

• a display panel comprising a plurality of gate lines, a plurality of data lines crossing and insulated from the plurality of gate lines, and a plurality of pixels respectively connected to the gate lines and the data lines;
• a data driver configured to provide data signals to the plurality of data lines;
• and
• a gate driver comprising a plurality of stages connected in cascade with each other and configured to provide gate signals to the plurality of gate lines,
• wherein an ith stage from among the plurality of stages, where i is an integer greater than or equal to two, comprises:
• a first output circuit configured to be turned on/off according to a potential of a first node, and to generate a gate signal from a clock signal received at an input terminal of the ith stage, the gate signal being outputted to a gate output terminal of the ith stage and including a gate on voltage and a gate off voltage;
• a first control circuit configured to control the potential of the first node;
• a first pull-down circuit configured to provide a first low voltage to the gate output terminal of the ith stage to drop down the gate signal of the ith stage, after the gate on voltage of the gate signal of the ith stage is outputted, the first low voltage being lower than the gate off voltage of the gate signal of the ith stage;
• a first holding circuit and a stabilization circuit, each configured to provide a second low voltage having a higher level than that of the first low voltage to the gate output terminal of the ith stage, after the first low voltage is provided to the gate output terminal of the ith stage;
• and
• a second control circuit configured to control an operation of the first holding circuit,
• wherein the first pull-down circuit comprises a first pull-down transistor, and the first pull-down transistor comprises a control electrode configured to receive an output signal of an i+1th stage, an input electrode configured to receive the first low voltage, and an output electrode connected to the gate output terminal.

A gate driving circuit comprising a plurality of stages configured to respectively output gate signals to gate lines and connected in cascade with each other, an ith stage from among the plurality of stages, where i is an integer greater than or equal to two, comprising:

• an output transistor comprising a control electrode connected to a first node, an input electrode configured to receive a clock signal, and an output electrode connected to an output terminal;
• a control transistor comprising a control electrode configured to receive an output of an i−1th stage, an input electrode connected to the control electrode, and an output electrode connected to the first node;
• a pull-down transistor comprising a control electrode configured to receive an output signal of an i+1th stage, an input electrode configured to receive a first low voltage, and an output electrode connected to the output terminal;
• a holding transistor comprising a control electrode connected to a second node, an input electrode configured to receive a second low voltage having a higher level than that of the first low voltage, and an output electrode connected to the output terminal;
• and
• a stabilization transistor comprising a control electrode configured to receive an output signal of an i+2th stage, an input electrode configured to receive the second low voltage, and an output electrode connected directly to the output terminal.