Scan driving circuit and display device

A scan driving circuit, comprising:

• a driving circuit, comprising a plurality of driving units connected in turn, wherein each of the driving units is correspondingly connected to a multiplexing circuit, each of the driving units comprises a first signal input end, a second signal input end, a first signal output end and a second signal output end, the first signal input end is employed to receive a trigger signal or a former stage scan signal, the second signal input end is employed to receive a latter stage scan signal, the first signal output end and the second signal output end are connected to the multiplexing circuit;
• and
• the multiplexing circuit, comprising a plurality of multiplexing units, wherein each of the multiplexing units comprises first to fifth signal receiving ends and a scan signal output end, the first signal receiving end is connected to the first signal output end of the driving unit, the second signal receiving end is connected to the second signal output end of the driving unit, the third signal receiving end is employed to receive a former stage scan signal, the fourth signal receiving end is employed to receive a latter stage scan signal, the fifth signal receiving end is employed to receive a clock signal, the scan signal output end is employed to output a scan signal to a scan line for driving a pixel unit;
• wherein each of the driving unit comprises first to fifth controllable switches and a first capacitor, a control end of the first controllable switch is connected to the first signal input end, a first end of the first controllable switch is connected to a voltage end, a second end of the first controllable switch is connected to a control end of the third controllable switch, a first end of the fourth controllable switch, a first end of the fifth controllable switch and the first signal output end, a control end of the second controllable switch is connected to a first end of the second controllable switch and the voltage end, a second end of the second controllable switch is connected to the second signal output end, a first end of the third controllable switch and a control end of the fourth controllable switch, second ends of the third to fifth controllable switches are all grounded, a control end of the fifth controllable switch is connected to the second signal input end, one end of the first capacitor is connected to a first end of the fifth controllable switch, the other end of the first capacitor is grounded.

A display device, comprising a scan driving circuit, wherein the scan driving circuit comprises:

• a driving circuit, comprising a plurality of driving units connected in turn, wherein each of the driving units is correspondingly connected to a multiplexing circuit, each of the driving units comprises a first signal input end, a second signal input end, a first signal output end and a second signal output end, the first signal input end is employed to receive a trigger signal or a former stage scan signal, the second signal input end is employed to receive a latter stage scan signal, the first signal output end and the second signal output end are connected to the multiplexing circuit;
• and
• the multiplexing circuit, comprising a plurality of multiplexing units, wherein each of the multiplexing units comprises first to fifth signal receiving ends and a scan signal output end, the first signal receiving end is connected to the first signal output end of the driving unit, the second signal receiving end is connected to the second signal output end of the driving unit, the third signal receiving end is employed to receive a former stage scan signal, the fourth signal receiving end is employed to receive a latter stage scan signal, the fifth signal receiving end is employed to receive a clock signal, the scan signal output end is employed to output a scan signal to a scan line for driving a pixel unit;
• wherein each of the driving unit comprises first to fifth controllable switches and a first capacitor, a control end of the first controllable switch is connected to the first signal input end, a first end of the first controllable switch is connected to a voltage end, a second end of the first controllable switch is connected to a control end of the third controllable switch, a first end of the fourth controllable switch, a first end of the fifth controllable switch and the first signal output end, a control end of the second controllable switch is connected to a first end of the second controllable switch and the voltage end, a second end of the second controllable switch is connected to the second signal output end, a first end of the third controllable switch and a control end of the fourth controllable switch, second ends of the third to fifth controllable switches are all grounded, a control end of the fifth controllable switch is connected to the second signal input end, one end of the first capacitor is connected to a first end of the fifth controllable switch, the other end of the first capacitor is grounded.