Shift register unit, gate driver circuit and display device

A shift register unit comprising:

• an input terminal, a reset terminal, a reference terminal, a first clock terminal, a second clock terminal, a third clock terminal, a first output terminal, a second output terminal,
• an input circuit for receiving an input signal from the input terminal and providing the input signal to a first node as a first level voltage;
• a first reset circuit for receiving a reference voltage from the reference terminal, and providing the reference voltage to the first node as a second level voltage in response to a reset signal from the reset terminal, the second level voltage being logically opposite to the first level voltage;
• a node control circuit for receiving a third clock signal from the third clock terminal and the reference voltage, and providing at a second node a second voltage signal logically opposite to a first voltage signal at the first node, the first voltage signal comprising a portion having the first level voltage and a portion having the second level voltage;
• a first output circuit for receiving a first clock signal from the first clock terminal and the reference voltage, and selectively providing the first clock signal or the reference voltage to the first output terminal in response to first voltage signal and the second voltage signal;
• and
• a second output circuit for receiving a second clock signal from the second clock terminal and the reference voltage, selectively providing the second clock signal or the reference voltage to the second output terminal in response to the first voltage signal and the second voltage signal, and maintaining a voltage difference between the first node and the second output terminal when the first node is floated,
• wherein the node control circuit comprises:
• a first node control circuit for providing the reference voltage to the first node in response to the second voltage signal;
• and
• a second node control circuit for providing at the second node the second voltage signal in response to the third clock signal and the first voltage signal.