Pixel circuit, display device, and method for driving same

A driving method of a display device, the display device including a plurality of data lines through which to transmit a plurality of analog voltage signals representing an image to be displayed;

• a plurality of write control lines intersecting the plurality of data lines;
• a plurality of display elements driven by a current and arranged in a matrix along the plurality of data lines and the plurality of write control lines;
• and a plurality of connection control transistors arranged to correspond to each of the plurality of data lines, each of the plurality of connection control transistors including a first conduction terminal connected to a corresponding data line, a second conduction terminal that receives an analog voltage signal to be applied to the corresponding data line, and a control terminal that receives a connection control signal to control switching on and off, the display device including a function of measuring a drive current to be applied to each display element, the method comprising:
• a connection control step of controlling switching on and off of the plurality of connection control transistors;
• a data line driving step of applying the analog voltage signal to the second conduction terminal of each of the plurality of connection control transistors;
• a write control line driving step of selectively driving the plurality of write control lines;
• a monitor control line driving step of selectively driving a plurality of monitor control lines arrayed to correspond to each of the plurality of write control lines;
• and
• a voltage fluctuation compensation line driving step of selectively driving a plurality of voltage fluctuation compensation lines arrayed to correspond to each of the plurality of write control lines, wherein
• the display device includes a plurality of pixel circuits arranged in the matrix along the plurality of data lines and the plurality of write control lines, each pixel circuit corresponding to any one of the plurality of data lines and corresponding to any one of the plurality of write control lines,
• each pixel circuit includes:
• an electro-optical element as a display element with a brightness controlled by a current;
• a voltage holding capacitor that holds a data voltage controlling a drive current of the electro-optical element;
• an input transistor including a control terminal connected to a corresponding write control line, the input transistor being a switching element that controls a voltage supply from a corresponding data line to the voltage holding capacitor;
• a drive transistor that applies a drive current corresponding to the data voltage to the electro-optical element;
• a monitor control transistor including a control terminal connected to a monitor control line corresponding to the corresponding write control line, the monitor control transistor being arranged between the drive transistor and the corresponding data line to allow a current flowing through the drive transistor to pass through;
• a voltage fluctuation compensation transistor including a control terminal connected to a voltage fluctuation compensation line corresponding to the corresponding write control line and a first conduction terminal connected to the corresponding data line, the voltage fluctuation compensation transistor being connected in series to the monitor control transistor;
• and
• a voltage fluctuation compensation capacitor defined between the first conduction terminal in the voltage fluctuation compensation transistor and the control terminal in the voltage fluctuation compensation transistor,
• in the data line driving step, the analog voltage signal is output from each output terminal of a data line drive circuit including a predetermined number of output terminals respectively corresponding to a plurality of sets of data line groups obtained by grouping the plurality of data lines where one set includes a predetermined number of two or more data lines, each output terminal is connected to a second conduction terminal of a predetermined number of connection control transistors corresponding to a predetermined number of data lines of a corresponding set,
• in the connection control step, a predetermined number of connection control signals respectively corresponding to a predetermined number of data lines of each set are generated and the predetermined number of connection control signals are respectively applied to the control terminals of the predetermined number of connection control transistors corresponding to a predetermined number of data lines of each set to thereby successively switch on the predetermined number of connection control transistors of each set for each predetermined period in a first selection period during which any one of the plurality of write control lines is in a selected state, and
• in the voltage fluctuation compensation line driving step, in the first selection period, after the plurality of connection control transistors are changed from an on state to an off state, a voltage to be applied to a voltage fluctuation compensation line corresponding to a write control line in the selected state changes from a first voltage to a second voltage to thereby change a voltage of the corresponding voltage fluctuation compensation line in direction opposite to a change of a voltage to be applied to a control terminal of the plurality of connection control transistors to change the plurality of connection control transistors from an on state to an off state.