Electrostatic discharge (ESD) and testing composite component, array substrate and display device

An electrostatic discharge (ESD) and testing composite component, wherein the composite component comprises a first signal line, a first thin-film transistor (TFT) and a second TFT which are electrically connected with the first signal line, a second signal line electrically connected with the first TFT, and a third signal line and a fourth signal line which are electrically connected with the second TFT;

• and the composite component is configured to provide a testing signal for the first signal line at a first stage and configured to provide ESD for the first signal line at a second stage;
• wherein the first TFT comprises a first gate electrode, a first source electrode and a first drain electrode, the first signal line is electrically connected with the first drain electrode and the second signal line is electrically connected with the first source electrode, or the first signal line is electrically connected with the first source electrode and the second signal line is electrically connected with the first drain electrode, and the first gate electrode is electrically connected with the first drain electrode or the first source electrode,
• wherein the second TFT comprises a second gate electrode, a second source electrode and a second drain electrode, the first signal line is electrically connected with the second source electrode and the third signal line is electrically connected with the second drain electrode, or the first signal line is electrically connected with the second drain electrode and the third signal line is electrically connected with the second source electrode, and the second gate electrode is electrically connected with the fourth signal line, and
• wherein the ESD and testing composite component further comprises a third TFT electrically connected with the first signal line and a fifth signal line electrically connected with the third TFT, the second TFT, the third signal line and the fourth signal line are configured to provide a testing signal for the first signal line at the first stage, and the first TFT, the third TFT, the second signal line and the fifth signal line are configured to provide ESD for the first signal line at the second stage.