Application processor including reconfigurable scaler and devices including the processor

A system comprising:

• a memory configured to store an image comprising first pixels;
• an application processor communicatively coupled with the memory;
• wherein the application processor comprises:
• a direct memory access (DMA) controller configured to read the first pixels from the memory;
• and
• a scaling technique selection register configured to select from different scaling techniques;
• a reconfigurable hardware scaler configured to support the different scaling techniques depending upon a pattern of the first pixels to be processed,
• wherein the reconfigurable hardware includes:
• dedicated circuits configured to perform different scaling techniques, respectively, and
• a shared circuit configured to be shared by the dedicated circuits,
• wherein the shared circuit comprises a computation circuit configured to scale the first pixels, and an analyzer circuit configured to analyze a pattern of second pixels relevant to the first pixels and to generate a selection signal that indicates a selection of one of the dedicated circuits;
• and
• wherein, based, at least in part, upon the scaling technique selection register, one of the different scaling techniques is performed by the selected one of the dedicated circuits and the shared circuit.

A data processing system comprising:

• a system on chip;
• and
• a display,
• wherein the system on chip comprises:
• a memory configured to store an image comprising first pixels, and
• an application processor connected to the memory;
• wherein the application processor comprises:
• a direct memory access (DMA) controller configured to read the first pixels from the memory, and
• a scaling technique selection register configured to select from different scaling techniques;
• a reconfigurable hardware scaler configured to support the different scaling techniques depending upon a pattern of the first pixels to be processed;
• and
• wherein the reconfigurable hardware scaler comprises:
• dedicated circuits configured to perform different scaling techniques, respectively, and
• a shared circuit configured to be shared by the dedicated circuits,
• wherein the shared circuit comprises a computation circuit configured to scale the first pixels, and an analyzer circuit configured to analyze a pattern of second pixels relevant to the first pixels and to generate a selection signal that indicates a selection of one of the dedicated circuits,
• wherein, based, at least in part, upon the scaling technique selection register, one of the different scaling techniques is performed by the selected one of the dedicated circuits and the shared circuit.