Alignment key design rule check for correct placement of abutting cells in an integrated circuit

A method of correcting a physical layout design by an electronic design tool executed by a computer for manufacture of an integrated circuit (IC), comprising:

• graphically placing, by the electronic design tool executed by the computer, a first alignment key shape on a first edge of a first cell and a second alignment key shape on a second edge of a second cell on an alignment layer created by the electronic design tool, the first edge and the second edge forming a common edge where the first cell abuts the second cell according to a physical layout design of an IC, the first alignment key shape and the second alignment key shape each comprising a number of elementary shapes, each elementary shape graphically representing one of:
• an allowed cell edge interaction and a disallowed cell edge interaction;
• checking, by the electronic design tool, a superimposition of an abutting alignment key shape, formed by graphically superimposing the first alignment key shape and the second alignment key shape on the alignment layer according to the physical layout design, by a design rule, to identify a disallowed cell placement of the first cell relative to the second cell when the superimposed abutting alignment key shape does not form a pre-defined abutting alignment key shape;
• graphically outputting, by the electronic design tool, the disallowed cell placement identified by the design rule on the alignment layer;
• substituting, by the design tool on the alignment layer, an allowed cell placement by another cell that has another alignment key shape and abuts the second cell along the common edge, to form the superimposition of the pre-defined abutting alignment key shape and provide a corrected physical layout design;
• and
• manufacturing the IC with the corrected physical layout design.

A computer program product readable by a computer tangibly embodying a program of instructions executable by the computer to perform a method of correcting a physical layout design by an electronic design tool executed by a computer for manufacture of an integrated circuit (IC), comprising:

• graphically placing, by the electronic design tool executed by the computer, a first alignment key shape on a first edge of a first cell having a first orientation and a second alignment key shape on a second edge of a second cell having a second orientation on an alignment layer created by the electronic design tool, the first edge and the second edge forming a common edge where the first cell abuts the second cell according to a physical layout design of IC;
• checking, by the electronic design tool, an abutting alignment key shape, formed by graphically placing the first alignment key shape and the second alignment key shape on the alignment layer according to the physical layout design, by a design rule to identify a disallowed cell placement of the first cell relative to the second cell when the abutting alignment key shape does not form a pre-defined abutting alignment key shape of a correct size;
• and
• graphically outputting, by the electronic design tool, the disallowed cell placement identified by the design rule on the alignment layer;
• substituting, by the design tool on the alignment layer, an allowed cell placement by another cell that has another alignment key shape and abuts the second cell along the common edge to form the pre-defined abutting alignment key shape of the correct size and provide a corrected physical layout design;
• and
• manufacturing the IC with the corrected physical layout design.