Pre-silicon design rule evaluation

A method for developing a set of design rules for a fabrication process, comprising:

• for each given one of a plurality of candidate design rule sets for the fabrication process,
• a computer system developing a layout of a logic cell in dependence upon the given design rule set, the logic cell having an input and an output and having at least a first transistor and at least a first interconnect connected to the first transistor,
• a computer system simulating fabrication of the logic cell according to the fabrication process and the layout, to derive a 3-dimensional model of the logic cell structure, the logic cell structure identifying geometry and materials composition of at least the first transistor and the first interconnect in the logic cell structure,
• a computer system characterizing by simulation behavior of the logic cell structure, including characterizing the combined behavior of both the first transistor and the first interconnect,
• a computer system evaluating performance of the logic cell structure in dependence upon the behavior as characterized;
• a computer system recording in a database on one or more computer readable media, in association with an indication of the given set of design rules, a set of one or more values indicating performance of the logic cell;
• the database being accessible to a user for use in optimizing the design rule sets for the fabrication process;
• and
• using the data recorded in the database as a basis for optimizing the design rule sets for the fabrication process,
• wherein characterizing by simulation behavior of the logic cell structure comprises:
• calibrating a second module that characterizes FETs by a second simulation model of transistor operation, to a first module that characterizes FETs by a first simulation model of transistor operation, the second module being quicker than the first module at characterizing a particular transistor, the calibrating yielding values for calibration parameters applicable to the second simulation model;
• and
• characterizing the behavior of the logic cell structure using the calibration parameter values.

A system for developing a set of design rules for a fabrication process, comprising:

• a layout module to develop a layout of a logic cell in dependence upon the given design rule set, the logic cell having an input and an output and having at least a first transistor and at least a first interconnect connected to the first transistor;
• a fabrication simulation module to simulate fabrication of the logic cell according to the fabrication process and the layout, to derive a 3-dimensional model of the logic cell structure, the logic cell structure identifying geometry and materials composition of at least the first transistor and the first interconnect in the logic cell structure;
• a logic cell simulation module to characterize behavior of the logic cell structure, including characterizing the combined behavior of both the first transistor and the first interconnect;
• an evaluation module to evaluate performance of the logic cell structure in dependence upon the behavior as characterized;
• a recording module to record in a database, in association with an indication of the given set of design rules, a set of one or more values indicating performance of the logic cell, the database being accessible to a user for use in optimizing the design rule sets for the fabrication process;
• a script executing module to operate the layout module, the fabrication simulation module, the logic cell simulation module, the evaluation module and the recording module for each given one of a plurality of candidate design rule sets for the fabrication process;
• and
• a module which uses the data recorded in the database as a basis for optimizing the design rule sets for the fabrication process.

A computer readable medium having stored thereon in a non-transitory manner, a plurality of software code portions defining logic for developing a set of design rules for a fabrication process, comprising:

• for each given one of a plurality of candidate design rule sets for the fabrication process,
• controlling a layout module to develop a layout of a logic cell in dependence upon the given design rule set, the logic cell having an input and an output and having at least a first transistor and at least a first interconnect connected to the first transistor;
• controlling a fabrication simulation module to simulate fabrication of the logic cell according to the fabrication process and the layout, to derive a 3-dimensional model of the logic cell structure, the logic cell structure identifying geometry and materials composition of at least the first transistor and the first interconnect in the logic cell structure;
• controlling a logic cell simulation module to characterize behavior of the logic cell structure, including characterizing the combined behavior of both the first transistor and the first interconnect;
• controlling an evaluation module to evaluate performance of the logic cell structure in dependence upon the behavior as characterized;
• controlling a recording module to record in a database, in association with an indication of the given set of design rules, a set of one or more values indicating performance of the logic cell, the database being accessible to a user for use in optimizing the design rule sets for the fabrication process,
• wherein the plurality of software code portions further define logic which uses the data recorded in the database as a basis for optimizing the design rule sets for the fabrication process.