System and method for power verification using efficient merging of power state tables

A power verification system, comprising:

• a storage medium for receiving and storing a description of at least a portion of an electronic circuit design having two or more power domains, and for receiving and storing a power intent file specifying a power architecture of power/voltage domains, their power supplies and corresponding power devices of the electronic circuit design, the power intent file comprising a plurality of power state tables that define allowed combinations of power states, and also for storing a report of power verification failures;
• a processor having access to the storage medium and executing an application program for a power verification tool that constructs merged power state tables corresponding to the power domains of the electronic circuit design and that uses the merged power state tables to verify whether the electronic circuit design complies with the power intent file;
• and
• a user interface including a computer display for displaying identified power verification failures and an input device for facilitating correction of at least one of the electronic circuit design and the power intent file;
• wherein the processor executing the application program (a) prepares to construct merged power state tables by removing power states from the power state tables in the power intent file by creating a scope tree representing a hierarchy of modules of the electronic circuit design with a root node being a top scope of the tree and, at every scope, while traversing the scope tree in a child-first, parent-next post order traversal, (i) creating a list of power state tables, (ii) for each pair of power state tables, removing any power states that are present in only one power state table, (iii) whenever there is a power state table list at child scope, adding power state tables from that list to a consolidated power state table list used in step (ii), and (iv) saving the consolidated power state table list for that scope;
• (b) constructs merged power state tables for pairs of power supplies of interest by selectively merging those power state tables that establish a relationship between the two power supplies of interest in the pair;
• and (c) displays on the computer display identified power verification failures and facilitates, using the input device, correction and storage of at least one of the description of the electronic circuit design and the power intent file.

A non-transitory computer readable storage medium containing an application program for a power verification tool that constructs power state tables for verification of power implementation of an electronic circuit design, the application program executable on a processor to perform a method comprising:

• accessing a power intent file that specifies a power architecture of power/voltage domains and their power supplies for an electronic circuit design, the power intent file comprising a plurality of power state tables that define allowed combinations of power states;
• preparing to construct merged power state tables by removing power states from the power state tables in the power intent file, comprising:
• creating a scope tree representing a hierarchy of modules of the electronic circuit design with a root node being a top scope of the tree;
• and
• at every scope, while traversing the scope tree in a child-first, parent-next post order traversal, (a) creating a list of power state tables, (b) for each pair of power state tables, removing any power states that are present in only one power state table, (c) whenever there is a power state table list at child scope, adding power state tables from that list to a consolidated power state table list used in step (b), and (d) saving the consolidated power state table list for that scope;
• constructing merged power state tables for pairs of power supplies of interest by selectively merging those power state tables that establish a relationship between the two power supplies of interest in the pair;
• and
• using the merged power state tables to verify whether the electronic circuit design complies with the power intent file.