Memory including side-car arrays with irregular sized entries

A system for generating on one or more masks a layout of an integrated circuit, the system comprising:

• a processor;
• and
• a non-transitory computer readable medium storing instructions, the instructions when executed by the processor causing the system to:
• generate layout data describing the integrated circuit, wherein to generate said layout the system is configured to:
• place a first portion of each memory line of a memory in a primary array of a memory macro block;
• place a second portion of each memory line in a sidecar array of the memory macro block, wherein the second portion is smaller than the first portion;
• determine a height of the sidecar array based on a notch in the memory macro block corresponding to a reserved area, wherein the height of the sidecar array is less than a height of the primary array;
• place the sidecar array in the memory macro block such that the notch is above or below the sidecar array when bit lines are oriented horizontally;
• generate on one or more integrated circuit masks a description of the layout data.

A computing system comprising:

• a processing unit;
• a memory comprising at least one memory macro block, wherein the at least one memory macro block comprises:
• a primary array storing a first portion of each memory line of the memory;
• a sidecar array storing a second portion of each memory line of the memory, wherein the second portion is smaller than the first portion;
• wherein a height of the sidecar array is based on a notch in the memory macro block corresponding to a reserved area, wherein the height of the sidecar array is less than a height of the primary array;
• and
• wherein the sidecar array is placed in the memory macro block such that the notch is above or below the sidecar array when bit lines are oriented horizontally;
• and
• control logic, wherein in response to receiving an access request corresponding to a first memory line from the processing unit, the control logic is configured to access both a first entry of a first plurality of entries in the primary array and a second entry of a second plurality of entries in the sidecar array based on a same address in the received access request.