Three-dimensional pattern risk scoring

A device comprising:

• a three dimensional (3D) simulator that generates a 3D simulation of semiconductor patterns;
• a processor configured to:
• obtain a set of critical dimensions of distances between layers or within a layer of the 3D model of semiconductor patterns;
• compare the set of critical dimensions with predefined minimum dimensions;
• and
• yield score, with non-linear models, each of the semiconductor patterns of the 3D simulation based on the comparing step,
• wherein the 3D simulation of semiconductor patterns represents an actual process outcome on a wafer,
• yield score each of the semiconductor patterns of the 3D simulation to generate an integrated circuit (IC) model, and
• wherein the IC yield model includes optimized parameters from design and process improvements.

A method comprising:

• generating, with a processor, a three dimensional (3D) simulation of semiconductor patterns representing an actual process outcome on a wafer;
• obtaining a set of critical dimensions of distances between layers or within a layer of the 3D simulation of semiconductor patterns;
• comparing the set of critical dimensions with predefined minimum dimensions;
• yield scoring each of the semiconductor patterns of the 3D simulation based on the comparing step to generate an integrated circuit (IC) model;
• normalizing an overall yield score to a volume of the 3D simulation of semiconductor patterns and translating it into a risk factor;
• identifying an at risk pattern prior to processing the IC model;
• and
• substituting the at risk pattern with an acceptable pattern,
• wherein the acceptable pattern has a lower risk factor than the at risk pattern,
• wherein the risk factor is a direct measure of a yield probability of the IC model, and
• wherein the 3D simulation of semiconductor patterns represents the actual process outcome on the wafer.