US 10,311,185 B2Granted

Model-building method and model-building system

AssigneesGlobal Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.

InventorsHsin-Hsiung Liao, Min-Hsiu Tsai

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Abstract

A model-building method and a model-building system for executing the method are disclosed. The method includes the following steps: reading a first netlist; extracting a netlist between an input and an initial-stage clock multi-vibrator and extracting a netlist between a final-stage clock multi-vibrator and an output from the first netlist; extracting a netlist between the input and the output from the first netlist; extracting a netlist between a first clock multi-vibrator and a second clock multi-vibrator from the first netlist; extracting netlists between the first clock input and the initial-stage clock multi-vibrator and the first clock multi-vibrator from the first netlist; extracting netlists between the second clock input and the final-stage clock multi-vibrator and the second clock multi-vibrator from the first netlist; and generating a second netlist based on extracted netlists.

Claims10

Dependent claims

A model-building method applied to a model-building system, wherein the model-building system comprises a memory and a processor, and the model-building method comprises:

reading a first netlist from the memory by using the processor;
extracting a first sub-netlist and a second sub-netlist from the first netlist by using the processor, wherein the first sub-netlist is between an input and an initial-stage clock multi-vibrator, the second sub-netlist is between a final-stage clock multi-vibrator and an output;
extracting a third sub-netlist from the first netlist by using the processor, the third sub-netlist being between the input and the output;
extracting a fourth sub-netlist from the first netlist by using the processor, the fourth sub-netlist being between a first clock multi-vibrator and a second clock multi-vibrator, wherein the first clock multi-vibrator is a front-stage clock multi-vibrator of the second clock multi-vibrator, the first clock multi-vibrator is coupled to a first clock input, and the second clock multi-vibrator is coupled to a second clock input;
extracting a fifth sub-netlist from the first netlist by using the processor, the fifth sub-netlist being between the first clock input and the initial-stage clock multi-vibrator or between the second clock input and the initial-stage clock multi-vibrator;
extracting a sixth sub-netlist from the first netlist by using the processor, the sixth sub-netlist being between the first clock input and the final-stage clock multi-vibrator or between the second clock input and the final-stage clock multi-vibrator;
extracting a seventh sub-netlist from the first netlist by using the processor, the seventh sub-netlist being between the first clock input and the first clock multi-vibrator;
extracting an eighth sub-netlist from the first netlist by using the processor, the eighth sub-netlist being between the second clock input and the second clock multi-vibrator;
and
generating a second netlist based on the first sub-netlist to the eighth sub-netlist that are extracted by using the processor.

7 more elements

A model-building system, comprising:

a memory configured to store a first netlist and a second netlist;
and
a processor configured to read the first netlist from the memory, wherein the processor is configured to execute the following operations to generate the second netlist:
extracting a first sub-netlist and a second sub-netlist from the first netlist, wherein the first sub-netlist is between an input and an initial-stage clock multi-vibrator, the second sub-netlist is between a final-stage clock multi-vibrator and an output;
extracting a third sub-netlist from the first netlist, the third sub-netlist being between the input and the output;
extracting a fourth sub-netlist from the first netlist, the fourth sub-netlist being between a first clock multi-vibrator and a second clock multi-vibrator, wherein the first clock multi-vibrator is a front-stage clock multi-vibrator of the second clock multi-vibrator, the first clock multi-vibrator is coupled to a first clock input, and the second clock multi-vibrator is coupled to a second clock input;
extracting a fifth sub-netlist from the first netlist, the fifth sub-netlist being between the first clock input and the initial-stage clock multi-vibrator or between the second clock input and the initial-stage clock multi-vibrator;
extracting a sixth sub-netlist from the first netlist, the sixth sub-netlist being between the first clock input and the final-stage clock multi-vibrator or between the second clock input and the final-stage clock multi-vibrator;
extracting a seventh sub-netlist from the first netlist, the seventh sub-netlist being between the first clock input and the first clock multi-vibrator;
and
extracting an eighth sub-netlist from the first netlist, the eighth sub-netlist being between the second clock input and the second clock multi-vibrator.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/709,463Filed 19 Sep 2017
Priority: CN 2017 1 033186212 May 2017
Published: US 2018/0330033 A115 Nov 2018
Granted: 4 Jun 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 30/327
Circuit design at the digital level: logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
G06F 30/33
Circuit design at the digital level: design verification, e.g. functional simulation or model checking
G06F 30/3312
Using simulation: timing analysis
G06F 30/3315
Design verification, e.g. functional simulation or model checking: using static timing analysis [STA]

Family

US 2018/0330033 A1Pre-grant publication · published 15 Nov 2018
US 10,311,185 B2This patent

From the US filing history. Foreign family members aren’t listed.

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