Circuit verification on a distributed database processing system

A non-transitory computer readable medium storing instructions for verifying a functionality of a design under test (DUT) corresponding to an integrated circuit, the instructions when executed by at least one processor causes the processor to:

• receiving, at a host system, from a hardware emulator comprising at least one field-programmable gate array (FPGA) configured to emulate the DUT, input waveform data including states of a signal of the DUT traced by the hardware emulator;
• divide, at the host system, the input waveform data for the DUT into input waveform segments;
• store the input waveform segments at a distributed database processing system in communication with the host system;
• generate analysis rules, each analysis rule associated with a corresponding one of the input waveform segments, each analysis rule describing how to determine a particular characteristic of a corresponding input waveform segment;
• store the analysis rules at the distributed database processing system, the distributed database processing system configured to map each input waveform segment to the corresponding analysis rule and generate analysis segments based on the input waveform segments and the corresponding analysis rules, each analysis segment indicating a characteristic of one or more corresponding input waveform segments;
• and
• retrieve, at the host system, an analysis result from the distributed database processing system, the analysis result representing an aspect of the functionality of the DUT, the analysis result generated at the distributed database processing system based on the analysis segments.

A system for verifying a functionality of a design under test (DUT) corresponding to an integrated circuit, the system comprising:

• a processor;
• and
• a memory comprising instructions executable by the processor, the instructions when executed by the processor cause the processor to:
• receiving, at a host system, from a hardware emulator comprising at least one field-programmable gate array (FPGA) configured to emulate the DUT, input waveform data including states of a signal of the DUT traced by the hardware emulator,
• divide, at the host system, the input waveform data into input waveform segments,
• store the input waveform segments at a distributed database processing system in communication with the host system,
• generate analysis rules, each analysis rule associated with a corresponding one of the input waveform segments, each analysis rule describing how to determine a particular characteristic of a corresponding input waveform segment,
• store the analysis rules at the distributed database processing system, the distributed database processing system configured to map each input waveform segment to the corresponding analysis rule and generate analysis segments based on the input waveform segments and the corresponding analysis rules, each analysis segment indicating a characteristic of one or more corresponding input waveform segments, and
• retrieve, at the host system, an analysis result from the distributed database processing system, the analysis result representing an aspect of the functionality of the DUT, the analysis result generated at the distributed database processing system based on the analysis segments.

A method of verifying functionality of a design under test (DUT) for manufacture of an integrated circuit, the method comprising:

• dividing an input waveform data for the DUT into input waveform segments, the input waveform data including states of a signal;
• storing the input waveform segments at a distributed database processing system;
• generating analysis rules, each analysis rule associated with a corresponding one of the input waveform segments, each analysis rule describing how to determine a particular characteristic of a corresponding input waveform segment;
• storing the analysis rules at the distributed database processing system, the distributed database processing system to generate analysis segments based on the input waveform segments and the analysis rules, each analysis segment representing a number of toggles within a corresponding input waveform segment according to the analysis rule;
• and
• retrieving an analysis result from the distributed database processing system, the analysis result representing a peak power consumption of the DUT, the analysis result generated at the distributed database processing system by (i) multiplying, for each of the analysis segments, the number of toggles with a corresponding coefficient to generate a corresponding power consumption value, and (ii) adding the power consumption values of the analysis segments.

A method of verifying functionality of a design under test (DUT) for manufacture of an integrated circuit, the method comprising:

• dividing an input waveform data for the DUT into input waveform segments, the input waveform data including states of a signal;
• storing the input waveform segments at a distributed database processing system;
• generating analysis rules, each analysis rule associated with a corresponding one of the input waveform segments, each analysis rule describing how to determine a particular characteristic of a corresponding input waveform segment;
• storing the analysis rules at the distributed database processing system, the distributed database processing system to generate analysis segments based on the input waveform segments and the analysis rules, each analysis segment representing a number of toggles within a corresponding input waveform segment according to the analysis rule;
• and
• retrieving an analysis result from the distributed database processing system, the analysis result representing an average power consumption of the DUT, the analysis result generated at the distributed database processing system by (i) multiplying, for each of the analysis segments, the number of toggles with a corresponding coefficient to generate a corresponding power consumption value, and (ii) obtaining an average of the power consumption values of the analysis segments.