High-speed inter-processor communications

A daughter board, comprising:

• a specialized processor;
• a high-speed inter-processor communications port connected to an additional high-speed inter-processor communications port of an additional daughter board through a high-speed inter-processor communications interconnect;
• and
• a standard interface for communicably connecting with a motherboard, wherein:
• the high-speed inter-processor communications port and the high-speed inter-processor communications interconnect conform to an industry standard;
• the industry standard is a QUAD SMALL FORM-FACTOR PLUGGABLE standard such that the high-speed inter-processor communications interconnect comprises a QUAD SMALL FORM-FACTOR PLUGGABLE cable that directly connects the high-speed inter-processor communications port to the additional high-speed inter-processor communications port of the additional daughter board;
• and
• the specialized processor is configured to directly access results of executing an application that are stored in a memory module of the additional daughter board across the high-speed inter-processor communications interconnect that connects the high-speed inter-processor communications port with the additional high-speed inter-processor communications port of the additional daughter board such that a bottleneck of a data path through a network card connected to the standard interface is bypassed.

A method performed by a specialized processor, comprising:

• receiving a signal to access a memory module;
• determining whether the memory module to be accessed is associated with a second daughter board on which the specialized processor is attached or a first daughter board;
• and
• in an event the memory module to be accessed is associated with the first daughter board, directly accessing results of executing an application that are stored in the memory module of the first daughter board across a high-speed inter-processor communications interconnect comprising a QUAD SMALL FORM-FACTOR PLUGGABLE cable that directly connects a high-speed inter-processor communications port of the first daughter board with a second high-speed inter-processor communications port of the second daughter board such that a bottleneck of a data path through a network card connected to a standard interface is bypassed.