US 10,311,007 B2Granted

Multicore bus architecture with non-blocking high performance transaction credit system

AssigneeTexas Instruments Incorporated

InventorsDavid M. Thompson, Timothy D. Anderson, Joseph R. M. Zbiciak, Abhijeet A. Chachad, Kai Chirca, Matthew D. Pierson

Life of this patent

Estimating the term…

patentgrep

Loading patent…

Abstract

This invention is a bus communication protocol. A master device stores bus credits. The master device may transmit a bus transaction only if it holds sufficient number and type of bus credits. Upon transmission, the master device decrements the number of stored bus credits. The bus credits correspond to resources on a slave device for receiving bus transactions. The slave device must receive the bus transaction if accompanied by the proper credits. The slave device services the transaction. The slave device then transmits a credit return. The master device adds the corresponding number and types of credits to the stored amount. The slave device is ready to accept another bus transaction and the master device is re-enabled to initiate the bus transaction. In many types of interactions a bus agent may act as both master and slave depending upon the state of the process.

Claims16

Dependent claims

A data processing system comprising:

a bus interface including a plurality of transaction attribute channels (TACs) that are credited channels and a plurality of transaction data channels (TDCs) that are non-credited channels;
a first logic unit coupled to the bus interface and including a first credit counter to indicate a respective count of each of a plurality of credit types, wherein each credit type corresponds to a respective one of a plurality of transaction types that the first logic unit is configured to initiate over the bus interface, and wherein the plurality of transaction types includes at least a first transaction type that includes transfer of data from the first logic unit;
and
a second logic unit coupled to the bus interface;
wherein the first logic unit is configured to operate as a master agent to initiate a first transaction that is of the first transaction type by sending transaction attribute information corresponding to the first transaction on a first TAC of the plurality of TACs, causing the first credit counter to decrement the count of the credit type corresponding the first transaction type, and sending data information corresponding to the first transaction on a first TDC of the plurality of TDCs;
and
wherein the second logic is configured to operate as a slave agent to accept the first transaction by receiving, on the first TAC, the transaction attribute information corresponding to the first transaction and receiving, on the first TDC, the data information corresponding to the first transaction.

4 more elements

A data processing system comprising:

a bus interface including a plurality of transaction attribute channels (TACs) that are credited channels;
a first logic unit coupled to the bus interface and including a first credit counter to indicate a respective count of each of a plurality of credit types, wherein each credit type corresponds to a respective one of a plurality of transaction types that the first logic unit is configured to initiate over the bus interface, wherein the first logic unit is configured to operate as a master agent to initiate a first transaction that is of a first transaction type of the plurality of transaction types by:
sending transaction attribute information corresponding to the first transaction on a first TAC of the plurality of TACs, the transaction attribute information including a credit type signal that indicates a credit type associated with the first transaction, wherein the credit type signal has a plurality of bits equal to a total number of the plurality of credit types;
and
decrementing the count of the credit type corresponding the first transaction type to reflect a spend of one credit of the credit type associated with the first transaction.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/903,183Filed 23 Feb 2018 · continuation
Priority: 31 Oct 2014
Published: US 2018/0293199 A111 Oct 2018
Granted: 4 Jun 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

G06F 13/42
Information transfer, e.g. on bus: bus transfer protocol, e.g. handshake; Synchronisation
G06F 13/364
With centralised access control: using independent requests or grants, e.g. using separated request and grant lines
G06F 13/404
Using bus bridges: with address mapping
G06F 13/4282
Bus transfer protocol, e.g. handshake; Synchronisation: on a serial bus, e.g. I2C bus, SPI bus

Family

Application14/530,203Parent of this continuation · filed 31 Oct 2014
US 2018/0293199 A1Pre-grant publication · published 11 Oct 2018
US 9,904,645 B2Parent of this continuation
US 2016/0124883 A1Published application
US 10,311,007 B2This patent

From the US filing history. Foreign family members aren’t listed.

Timeline

Citations

Open elsewhere

Building an agent or pulling many patents? Use the API or MCP server instead of scraping pages. Get an API key