Efficient memory virtualization in multi-threaded processing units

A parallel processor configured to map virtual addresses associated with a first virtual address space included in a set of different virtual address spaces to a physical address, the parallel processor comprising:

• a memory management unit that:
• receives a memory access request transmitted by a first thread program, wherein the memory access request, when transmitted by the first thread program, includes both a virtual address and an address space identifier (ASID) associated with the first virtual address space;
• determines that no entry included in a first translation look aside buffer (TLB) included in a plurality of TLBs matches both the ASID and the virtual address included in the memory access request, resulting in a TLB miss;
• in response to the TLB miss, maps the virtual address included in the memory access request to a physical address by:
• mapping the ASID to a physical address reference that points to a page table residing in memory;
• and
• mapping the virtual address to the physical address via the page table;
• and
• associates the physical address with the memory access request,
• wherein the first TLB is associated with a first streaming multiprocessor included in a plurality of streaming multiprocessors.

A computing device, comprising:

• a central processing unit configured to execute a process having a first processing context;
• and
• a parallel processor couple to the central processing unit and including a memory management unit that:
• receives a memory access request transmitted by a first thread program,
• wherein the memory access request, when transmitted by the first thread program, includes both a virtual address and an address space identifier (ASID) associated with the first virtual address space;
• determined that no entry included in a first translation look aside buffer (TLB) included in a plurality of TLBs matches both the ASID and the virtual address included in the memory access request, resulting in a TLB miss;
• in response to the TLB miss, maps the virtual address included in the memory access request to a physical address by:
• mapping the ASID to a physical address reference that points to a page table residing in memory;
• and
• mapping the virtual address to the physical address via the page table;
• and
• associates the physical address with the memory access request,
• wherein the first TLB is associated with a first streaming multiprocessor included in a plurality of streaming multiprocessors.