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US 10,310,942 B2Granted
Memory system
AssigneeToshiba Memory Corporation
InventorsMarie Takada, Masanobu Shirakawa
Life of this patent
Estimating the term…
Abstract
A memory system includes: a semiconductor memory device; and a controller. When receiving the first read instruction, the semiconductor memory device issues a strobe signal at a first timing to read data from the first memory cell and the second memory cell. When receiving the second read instruction, the semiconductor memory device sets the first memory cell to a non-read target and reads data from the second memory cell based on a strobe result of the data at the first timing.
Claims20
A memory system comprising:
- a semiconductor memory device including a memory cell array;
- and
- a controller capable of issuing a first read instruction and a second read instruction different, from the first read instruction, wherein the memory cell array includes:
- a first memory cell and a second memory cell;
- a first bit line connected to the first memory cell;
- and
- a second bit line connected to the second memory cell, and
- wherein when receiving the first read instruction, the semiconductor memory device applies a first voltage to the first bit line and the second bit line and issues a strobe signal at a first timing to read data from the first memory cell and the second memory cell, and
- when receiving the second read instruction, the semiconductor memory device applies a second voltage different from the first voltage to the first bit line to set the first memory cell to a non-read target and applies the first voltage to the second bit line to read data from the second memory cell based on a strobe result of the data at the first timing.
6 more elements
A memory system comprising:
- a semiconductor memory device including a memory cell array and configured to read data from the memory cell array in units of page;
- and
- a controller capable of issuing a first read instruction to read first page data from the semiconductor memory device and a second read instruction different from the first read instruction,
- wherein the one page data is determined using a plurality of read levels,
- when receiving the first read instruction, the semiconductor memory device issues a strobe signal a first number of times, and
- when receiving the second read instruction, the semiconductor memory device issues the strobe signal a second number of times, and
- the first number of times is a natural number not less than 2, and the second number of times is smaller than the first number of times.
4 more elements
A memory system comprising:
- a semiconductor memory device including a memory cell array;
- and
- a controller capable of issuing a first read instruction to read data from the semiconductor memory device in units of page and a second read instruction different from the first read instruction,
- wherein the memory cell array includes:
- a first memory cell;
- and
- a first, word line connected to the first memory cell, and
- wherein when receiving the first read instruction from the controller, the semiconductor memory device sequentially applies a first voltage and a second voltage different from the first voltage to the first word line and strobes data for each voltage to determine data of a first page, and sets data obtained using the strobe result when the first voltage is used without using the strobe result when the second voltage is used, and
- when receiving the second read instruction from the controller, the semiconductor memory device applies a third voltage different from the first voltage and the second voltage to the first word line to strobe data, and determines data of the first page based on the strobe result and the data in the latch circuit.
6 more elements
Dependencies are inferred from the claim text.