Temporary pipeline marking for processor error workarounds

A computer system for temporary pipeline marking for processor error workarounds, the computer system comprising:

• a processor configured to perform a method comprising:
• monitoring an execution unit pipeline of the processor for an event that is predetermined to cause a stuck state that results in an errant instruction execution result due to the stuck state, wherein the event is associated with a programmable instruction operational code;
• marking the execution unit pipeline for a workaround action based on detecting the event;
• triggering a clearing action based on the marking of the execution unit pipeline, wherein the triggering is conditionally triggered by a next instruction in the execution unit pipeline having a same instruction type as the programmable instruction operational code;
• and
• clearing the marking of the pipeline based on the triggering of the clearing action, wherein the clearing action is a subsequent pipeline flush event based on the next instruction having the same instruction type reaching a same pipeline stage that results in a stuck state prior to completion of the next instruction.

A computer program product for temporary pipeline marking for processor error workarounds, the computer program product comprising:

• a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code executable to perform:
• monitoring an execution unit pipeline of a processor for an event that is predetermined to cause a stuck state that results in an errant instruction execution result due to the stuck state, wherein the event is associated with a programmable instruction operational code;
• marking the execution unit pipeline for a workaround action based on detecting the event;
• triggering a clearing action based on the marking of the execution unit pipeline, wherein the triggering is conditionally triggered by a next instruction in the execution unit pipeline having a same instruction type as the programmable instruction operational code;
• and
• clearing the marking of the pipeline based on the triggering of the clearing action, wherein the clearing action is a subsequent pipeline flush event based on the next instruction having the same instruction type reaching a same pipeline stage that results in a stuck state prior to completion of the next instruction.