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US 10,310,895 B2Granted
Memory-based software barriers
AssigneeIntel Corporation
InventorsAltug Koker, Joydeep Ray, Balaji Vembu, James A. Valerio, Abhishek R. Appu
Life of this patent
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Abstract
A mechanism is described for facilitating memory-based software barriers to emulate hardware barriers at graphics processors in computing devices. A method of embodiments, as described herein, includes facilitating converting thread scheduling at a processor from hardware barriers to software barriers, where the software barriers emulate the hardware barriers.
Claims14
An apparatus comprising:
- one or more processors including a graphics processor, the graphics processor including a plurality of hardware barriers;
- and
- a graphics data port unit;
- wherein the one or more processors are to:
- schedule a plurality of threads for processing, including assigning one or more hardware barriers of the plurality of hardware barriers to one or more thread groups;
- track barrier resources for thread scheduling, including tracking of whether each assigned barrier is a hardware barrier or a software barrier;
- upon determining based on the tracking of barrier resources that a number of available hardware barriers is insufficient for scheduling of threads, assign one or more software barriers to a first thread group to emulate operation of one or more hardware barriers;
- perform handling of the one or more software barriers in the graphics processor using the graphics data port unit without necessitating changes to an application programming interface (API) or a compiler associated with the one or more processors;
- and
- transmit a barrier message to the graphics data port unit, the barrier message including one or more attribute bits to indicate the one or more software barriers and including a respective memory address for each of the one or more software barriers.
7 more elements
A method comprising:
- scheduling a plurality of threads for processing at one or more processors including a graphics processor, the graphics processor including a plurality of hardware barriers, wherein scheduling includes assigning one or more hardware barriers of the plurality of hardware barriers to one or more thread groups;
- tracking barrier resources for thread scheduling, including tracking of whether each assigned barrier is a hardware barrier or a software barrier;
- upon determining based on the tracking of barrier assignments that a number of available hardware barriers is insufficient for scheduling of threads, assigning one or more software barriers to a first thread group to emulate operation of one or more hardware barriers;
- performing handling of the one or more software barriers in the graphics processor using a graphics data port unit without necessitating changes to an application programming interface (API) or a compiler associated with the one or more processors;
- and
- transmitting a barrier message to the graphics data port unit, the barrier message including one or more attribute bits to indicate the one or more software barriers and including a respective memory address for each of the one or more software barriers.
3 more elements
At least one non-transitory machine-readable medium comprising instructions that when executed by a computing device, cause the computing device to perform operations comprising:
- scheduling a plurality of threads for processing at one or more processors including a graphics processor, the graphics processor including a plurality of hardware barriers, wherein scheduling includes assigning one or more hardware barriers of the plurality of hardware barriers to one or more thread groups;
- tracking barrier resources for thread scheduling, including tracking of whether each assigned barrier is a hardware barrier or a software barrier;
- upon determining based on the tracking of barrier resources that a number of available hardware barriers is insufficient for scheduling of threads, assign one or more software barriers to a first thread group to emulate operation of one or more hardware barriers;
- performing handling of the one or more software barriers in the graphics processor using a graphics data port unit without necessitating changes to an application programming interface (API) or a compiler associated with the processor;
- and
- transmitting a barrier message to the graphics data port unit, the barrier message including one or more attribute bits to indicate the one or more software barriers and including a respective memory address for each of the one or more software barriers.
3 more elements
Dependencies are inferred from the claim text.