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US 10,310,861 B2Granted
Mechanism for scheduling threads on a multiprocessor
AssigneeIntel Corporation
InventorsBalaji Vembu, Abhishek R. Appu, Joydeep Ray, Altug Koker
Life of this patent
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Abstract
An apparatus to facilitate thread scheduling is disclosed. The apparatus includes logic to store barrier usage data based on a magnitude of barrier messages in an application kernel and a scheduler to schedule execution of threads across a plurality of multiprocessors based on the barrier usage data.
Claims17
An apparatus comprising:
- a processor to analyze an application kernel to determine a magnitude of barrier messages in the application kernel and generate barrier usage data having a value corresponding to the magnitude of barrier messages in the application kernel;
- a memory to store the barrier usage data;
- and
- a graphics processor, including:
- a plurality of multiprocessors;
- and
- a scheduler to retrieve the barrier usage data from the memory and to schedule execution of each thread of a plurality of threads to a respective microprocessor of the plurality of multiprocessors according to a scheduling policy, the scheduling policy being based at least in part on the barrier usage data, wherein the scheduler is to prioritize scheduling threads of a thread group to a same microprocessor of the plurality of multiprocessors upon a determination that the barrier usage data indicates a high magnitude of barrier messages in the thread group.
4 more elements
A method comprising:
- analyzing an application kernel during compiling to determine a magnitude of barrier messages in the application kernel;
- generating barrier usage data during the compiling having a value corresponding to the magnitude of barrier messages in the application kernel;
- receiving a plurality of threads for scheduling;
- and
- scheduling execution of each thread of the plurality of threads to a respective microprocessor of a plurality of multiprocessors according to a scheduling policy, the scheduling policy being based at least in part on the barrier usage data, wherein scheduling includes prioritizing the scheduling of threads of a thread group for execution to a same microprocessor of the plurality of multiprocessors upon a determination that the barrier usage data indicates a high magnitude of barrier messages in the thread group.
2 more elements
A non-transitory computer readable medium having instructions, which when executed by one or more processors, cause the processors to perform operations comprising:
- analyzing an application kernel during compiling to determine a magnitude of barrier messages in the application kernel;
- generating barrier usage data during the compiling having a value corresponding to the magnitude of barrier messages in the application kernel;
- receiving a plurality of threads for scheduling;
- and
- scheduling execution of each thread of the plurality of threads to a respective microprocessor of a plurality of multiprocessors according to a scheduling policy, the scheduling policy being based at least in part on the barrier usage data, wherein scheduling includes prioritizing the scheduling of threads of a thread group for execution to a same microprocessor of the plurality of multiprocessors upon a determination that the barrier usage data indicates a high magnitude of barrier messages in the thread group.
2 more elements
Dependencies are inferred from the claim text.