Starting and stopping instruction dispatch to execution unit queues in a multi-pipeline processor

A computer processor core comprising:

• an issuer for issuing decoded instructions;
• a plurality of queues that receive the decoded instructions from the issuer;
• a dispatcher that dispatches the decoded instructions from the plurality of queues to a plurality of execution units;
• and
• a dispatch adjust circuit that receives queue full signals comprising a queue full signal from each of the plurality of queues and in response to the queue full signals sends a stop signal;
• wherein the issuer, in response to the stop signal, stops sending decoded instructions to the plurality of queues;
• and
• wherein the dispatch adjust circuit further receives queue empty signals comprising a queue empty signal from each of the plurality of queues, and in response to the queue empty signals indicating all of the plurality of queues are empty, sends a start signal to restart sending decoded instructions to the plurality of queues.