Systems and methods facilitating multi-word atomic operation support for system on chip environments

A system on chip, comprising:

• a central processing unit configured to execute an instruction defined by message data associated with a calling process, the message data comprising an opcode field defining a plurality of operations to be performed in accordance with the instruction and an operand field defining a plurality of values used as operands for the plurality of operations;
• and
• an atomic engine component coupled to the central processing unit and configured to:
• receive the message data;
• determine a first memory width associated with execution of the instruction based on types of the plurality of operations defined by the opcode field and widths of the plurality of values defined by the operand field, wherein the atomic engine component is further configured to determine the first memory width by:
• determining based on analysis of the message data, a quantity of the plurality of values defined by the operand field and types of the plurality of values defined by the operand field;
• and
• determining the first memory width as a function of the quantity and the type;
• and
• reserve and lock a memory location comprising a second memory width that is greater than the first memory width,
• wherein the atomic engine component comprises circuitry configured to perform the plurality of operations as multi-word atomic operations on a memory of the system on chip.

A method comprising:

• receiving, by a system-on-chip, information defining an instruction associated with a calling process, the information comprising an opcode field defining a plurality of operations to be performed as part of the instruction and an operand field defining a plurality of values used to execute the plurality of operations;
• determining, by the system-on-chip, a first memory width associated with execution of the instruction based on identities of the plurality of operations defined by the opcode field and widths of the plurality of values defined by the operand field, wherein the determining comprises:
• determining, based on analysis of the information, a quantity of the plurality of values defined by the operand field and types of the plurality of values defined by the operand field, and
• determining the first memory width as a function of the quantity and the type;
• and
• locking, by the system-on-chip, a memory location comprising a second memory width that is greater than the first memory width, wherein the system-on-chip comprises circuitry configured to perform one or more operations to facilitate multi-word atomic support for the system on chip.