US 10,310,734 B2Granted

Tier mode for access operations to 3D memory

AssigneeIntel Corporation

InventorToru Tanzawa

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Abstract

Tier access mode for three dimensional (3D) memory devices. A 3D memory device has multiple memory elements that are each addressable by a two dimensional address including a wordline address and a bitline address, and a third dimension with a sub-block selector indicating one of multiple portions of a tier of memory elements in the memory device. A memory controller generates a memory access command, such as read or program, to access a first portion of the memory and sends the command to the memory device. The memory device charges a first wordline and a first sub-block in response to receiving the command. For a consecutive access command to access a second portion of the memory, the memory device maintains the first wordline charged without discharging it, and charges a second sub-block selector in response to the consecutive command.

Claims20

Dependent claims

A three dimensional (3D) memory device, comprising:

multiple memory elements stacked in multiple tiers of wordlines, the memory elements addressable with a bitline address, a wordline address, and a sub-block address;
and
logic to:
receive a first command and a second command to access different portions of a first wordline from a memory controller;
in response to receipt of the first command, charge a first wordline, a first bitline, and a first sub-block to select a first portion of the first wordline, and discharge the first bitline and the first sub-block, but not the first wordline, after the access to the first portion;
in response to receipt of the second command after the first command, to maintain charge to the first wordline without the first wordline being discharged and recharged, and charge a second bitline and a second sub-block to select a second portion of the wordline, and after the access to the second portion, discharge the second bitline and the second sub-block, but not the first wordline;
receive a third command to access a second wordline from the memory controller, the memory controller to send the third command only after a determination that a last sub-block of the first wordline has been accessed;
and
in response to receipt of a third command, discharge the first wordline, charge the second wordline, a third bitline, and a third sub-block to select a portion of the second wordline.

6 more elements

A memory controller for accessing data in a three dimensional (3D) memory device, comprising:

logic to:
receive a request to read or write data to the 3D memory device;
identify a first portion of the data with a first wordline address, a first bitline address, and a first sub-block selector;
generate a first command to access the first portion of the data;
identify a second portion of the data with the first wordline address and a second sub-block selector;
generate a second command to access the second portion of the data;
determine whether a last sub-block of the first wordline has been accessed;
in response to a determination that the last sub-block of the first wordline has been accessed, identify a third portion of the data with a second wordline address;
generate a third command to access the third portion of the data;
and
I/O (input/output) circuitry to:
send the first command to the memory device to cause the memory device to charge a first wordline, a first bitline, and a first sub-block, and after the access to the first portion of the data, discharge the first bitline and the first sub-block, but not the first wordline;
send the second command to the memory device to cause the memory device to maintain charge to the first wordline;
and
send the third command to the memory device only after the determination that the last sub-block of the first wordline has been accessed, the third command to cause the memory device to discharge the first wordline and charge a second wordline.

12 more elements

A system comprising:

a three dimensional (3D) memory device including multiple memory elements, the memory elements addressable with a bitline address, a wordline address, and a sub-block selector;
a memory controller coupled to the memory device, the memory controller including:logic to:
receive a request to read or write data to the 3D memory device;
identify a first portion of the data with a first wordline address, a first bitline address, and a first sub-block selector;
generate a first command to access the first portion of the data;
identify a second portion of the data with the first wordline address and a second sub-block selector;
generate a second command to access the second portion of the data;
determine whether a last sub-block of the first wordline has been accessed;
in response to a determination that the last sub-block of the first wordline has been accessed, identify a third portion of the data with a second wordline address;
generate a third command to access the third portion of the data;
and
I/O (input/output) circuitry to:
send the first command to the memory device to cause the memory device to charge a first wordline, a first bitline, and a first sub-block, and after the access to the first portion of the data, discharge the first bitline and the first sub-block, but not the first wordline;
send the second command to the memory device to cause the memory device to maintain charge to the first wordline;
and
send the third command to the memory device only after the determination that the last sub-block of the first wordline has been accessed, the third command to cause the memory device to discharge the first wordline and charge a second wordline;
and
a touchscreen display coupled to generate a display based on data accessed from the memory device.

15 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/583,626Filed 27 Dec 2014
Published: US 2016/0188210 A130 Jun 2016
Granted: 4 Jun 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

G06F 3/0604
Specifically adapted to achieve a particular effect: improving or facilitating administration, e.g. storage management
G06F 3/0659
Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices: command handling…
G06F 3/068
Single storage device: hybrid storage device
G11C 7/00
Arrangements for writing information into, or reading information out from, a digital

Family

US 2016/0188210 A1Pre-grant publication · published 30 Jun 2016
US 10,310,734 B2This patent

From the US filing history. Foreign family members aren’t listed.

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