Forcing core low power states in a processor
AssigneeIntel Corporation
InventorsAnkush Varma, Krishnakanth V. Sistla, Allen W. Chu, Ian M. Steiner
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Abstract
In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a power delivery logic coupled to the plurality of cores, and a power controller including a first logic to cause a first core to enter into a first low power state of an operating system power management scheme independently of the OS, during execution of at least one thread on the first core. Other embodiments are described and claimed.
Claims17
A processor comprising:
- a semiconductor die comprising:
- a plurality of cores;
- a plurality of integrated voltage regulators coupled to the plurality of cores;
- and
- a power controller including a first hardware logic to cause, in response to a power consumption level of the processor that exceeds a threshold level, a first core of the plurality of cores to enter into a first inactive low power state of an operating system power management (OSPM) scheme independently of and transparently to the OS, during execution of at least one thread on the first core and without a request from the first core, wherein the first hardware logic is to send a first low power force signal to the first core to cause the first core to prepare for entry into the first inactive low power state during the at least one thread execution and send a second low power force signal to a first voltage regulator of the plurality of integrated voltage regulators to cause the first voltage regulator to be turned off after the first core is prepared for the entry into the first inactive low power state.
A non-transitory machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
- sending, from a power controller of a processor, a core offline request to an operating system (OS) in response to a power consumption level of the processor exceeding a threshold level, the core offline request to cause the OS to stop scheduling work to at least one core of the processor;
- thereafter receiving, in the power controller, a low power state request from the OS;
- and
- responsive to the low power state request, causing the at least one core to enter into the low power state comprising an offline state, and maintaining the at least one core in the low power state for at least a first time duration.
A system comprising:
- a processor including a plurality of cores, one or more internal voltage regulators, and a power controller, responsive to a determination that a power consumption level of the processor has exceeded a first threshold, to initiate entry of a first core of the plurality of cores into a low power state during execution of a thread on the first core, and to send an offline request to an operating system (OS) to cause the OS to terminate thread scheduling to the first core for at least a first time duration to scale a number of cores of the plurality of cores available to the OS, wherein after the first thread is completed, the power controller is cause the first core to enter into the low power state responsive to a low power state request received from the OS after the offline request is sent to the OS, and maintain the first core in the low power state for at least the first time duration;
- an external voltage regulator coupled to the processor;
- and
- a dynamic random access memory (DRAM) coupled to the processor.
Dependencies are inferred from the claim text.