Memory power savings in idle display case

An apparatus comprising:

• a plurality of components;
• a memory system coupled to the plurality of components;
• a memory cache coupled to the memory system and configured to cache data accessed in the memory system by the plurality of components, wherein the memory cache is checked for a hit prior to accessing the memory system in response to a memory operation, wherein the memory system is not accessed and the memory cache is accessed in response to the hit for a memory operation, wherein the plurality of components comprise one or more central processing unit (CPU) processors, and wherein a portion of the memory data cached in the memory cache is CPU data accessed by the one or more CPU processors;
• and
• a display controller coupled to the memory cache and the memory system, wherein the display controller is configured to generate memory operations to read at least one frame buffer stored in the memory system to display images on a display device, and wherein the memory cache is programmed during use to disable the memory cache from entering a power down state responsive to the images on the display device being static, and wherein the memory cache is programmed, during use, to disable memory cache automatic resizing responsive to the images on the display device being static, whereby the memory cache remains full size responsive to disabling of memory cache automatic resizing, and wherein the memory cache is programmed, during use, to enable memory cache automatic resizing responsive to the images displayed by the display controller being dynamic.

A non-transitory computer accessible storage medium storing a plurality of instructions executable by one or more processors in an integrated circuit that also includes a display controller, a memory controller that includes a memory cache, a plurality of components including one or more central processing unit (CPU) processors, and a power manager circuit, the plurality of instructions including:

• a power manager driver corresponding to the power manager circuit;
• a memory driver corresponding to the memory controller;
• and
• a display driver corresponding to the display controller, wherein the display driver detects that images being displayed by the display controller are static, and wherein the memory driver disables a memory cache power down state responsive to the static images, and wherein the memory cache is configured to cache data read from memory by the plurality of components, including the one or more CPU processors, wherein the memory controller checks the memory cache for a hit for the memory operations from the plurality of components, and the memory controller does not access the memory and accesses the memory cache in response to the hit for a given memory operation, and wherein the memory driver disables memory cache automatic resizing responsive to the static images, whereby the memory cache remains full size responsive to disabling memory cache automatic resizing, and wherein the display driver detects that the images being displayed are dynamic, and wherein the memory driver enables the memory cache automatic resizing responsive to the dynamic images.