Voltage level detection and analog circuit arrangements for memory systems

A method comprising:

• receiving, with a core regulator, a host supply voltage from a host system;
• receiving, with host interface circuitry, a host clock signal on a host clock line during a predetermined time period;
• receiving, with the host interface circuitry, a synchronization command from the host system upon expiration of the predetermined time period;
• detecting, with host clock detection circuitry, a presence of the host clock signal on the host clock line during the predetermined time period;
• in response to detecting the presence of the host clock signal during the predetermined time period:
• detecting, with host supply voltage detection circuitry, a level of the host supply voltage;
• supplying, with the core regulator, a core supply voltage as a regulated voltage or an unregulated voltage to core logic circuitry based on detecting the level of the host supply voltage;
• and
• sending, with power on detection circuitry, a core voltage stabilization signal to the core logic, the core voltage stabilization signal indicating that the core supply voltage is stable.

An apparatus comprising:

• host interface circuitry configured to:
• receive a host clock signal on a host clock line during a predetermined time period;
• receive a synchronization command from a host system upon expiration of the predetermined period;
• host clock detection circuitry configured to:
• detect a presence of the host clock signal on the host clock line within the predetermined time period;
• send a notification indicating that the presence of the host clock signal has been detected;
• host supply voltage detection circuitry configured to:
• receive the notification from the host clock detection circuitry that the presence of the host clock signal has been detected;
• determine to detect a level of a host supply voltage in response to receipt of the notification that the host clock signal has been detected;
• detect the level of a host supply voltage in response the determination;
• and
• in response to the detected level, output a control signal indicating whether a core supply voltage is to be output as either a regulated voltage or an unregulated voltage;
• and
• a core regulator configured to:
• receive the control signal from the host supply voltage detection circuitry;
• and
• supply the core supply voltage as the regulated voltage or the unregulated voltage to core logic circuitry in response to receipt of the control signal,
• wherein the core regulator is configured to monitor the core supply voltage using feedback in order to supply the core supply voltage as the regulated voltage, and
• wherein the core regulator is configured to bypass the supply voltage directly to an output of the core regulator in order to output the core supply voltage as the unregulated voltage;
• and
• power on detection circuitry configured to:
• receive the control signal;
• and
• in response to receipt of the control signal, send a notification to the core logic circuitry indicating that the level of the host supply voltage is stable.