Arbitrary waveform generator based on instruction architecture

An arbitrary waveform generator based on instruction architecture, comprising:

• a host computer for generating a corresponding waveform synthesis instruction based on the waveform characteristics input by user;
• a synthesis device for performing waveform synthesis according to the waveform synthesis instruction generated by the host computer, and outputting a complex sequence wave;
• wherein the synthesis device comprises an instruction set based waveform synthesis controller (hereinafter referred as waveform synthesis controller), a memory, a storage control module, a DMA control module, a FIFO module, an output control module, a digital-analog conversion module and an output conditioning module;
• the waveform synthesis instruction generated by the host computer is sent to the synthesis device, and received by the waveform synthesis controller;
• after receiving the waveform synthesis instruction, the waveform synthesis controller parses the waveform synthesis instruction into a trigger control command and a DMA command, and the trigger control command is sent to the output control module, the DMA command is sent to the DMA control module;
• the DMA control module receives and parses the DMA command to get a waveform data read control command, and sends the waveform data read control command to the storage control module;
• the storage control module addresses in the memory according to the waveform data read control command, and transfers the waveform data of the corresponding segment address, i.e. segment waveform data to the FIFO module through the DMA control module;
• the segment waveform data is buffered by the FIFO module, then sent to the output control module;
• according to an inputted trigger signal and a trigger control command, the output control module completes the trigger function of the waveform data generation, and sends the segment waveform data to the digital-analog conversion module continuously;
• the digital-analog conversion module converts the segment waveform data into an analog signal, and then the analog signal is conditioned, i.e. filtered, amplified or attenuated through the output conditioning module to obtain the complex sequence wave, thus the waveform synthesis is completed;
• wherein the waveform synthesis controller comprises an instruction buffer, an instruction parser, an instruction address generator and a data address generator;
• where the instruction buffer is used for storing the waveform synthesis instruction sent by the host computer, fetching out the waveform synthesis instruction which needs to be executed according to the instruction address sent by the instruction address generator, and sending the waveform synthesis instruction to the instruction parser;
• the instruction parser parses the waveform synthesis instruction into a flow control command, a segment waveform control command and a trigger control command;
• the flow control command is sent to the instruction address generator, the segment waveform control command is sent to the data address generator;
• the trigger control command is sent to the output control module;
• the instruction address generator generates an instruction address of the next waveform synthesis instruction for the instruction buffer, executing the waveform synthesis instruction in sequence, or in jump according to the flow control command;
• the data address generator generates a DMA command according to the segment waveform control command sent by the instruction parser, and sends the DMA command to the DMA control module, thus the reading control of a segment waveform data is completed.