Variation-tolerant voltage reference
AssigneeThe Regents of the University of Michigan
InventorsQing Dong, David T. Blaauw, Dennis Sylvester
Life of this patent
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Abstract
A sub-nW voltage reference is presented that provides inherently low process variation and enables trim-free operation for low-dropout regulators and other applications in nW microsystems. Sixty chips from three different wafers in 180 nm CMOS are measured, showing an untrimmed within-wafer σ/μ of 0.26% and wafer-to-wafer σ/μ of 1.9%. Measurement results also show a temperature coefficient of 48-124 ppm/° C. from −40° C. to 85° C. Outputting a 0.986V reference voltage, the reference operates down to 1.2V and consumes 114 pW at 25° C.
Claims17
A voltage reference circuit, comprising:
- a first metal-oxide semiconductor field-effect transistor (MOSFET) having a source terminal, a drain terminal, a gate terminal and a body terminal, where the gate terminal of the first MOSFET is directly coupled to the source terminal of the first MOSFET and the body terminal of the first MOSFET is biased with a voltage that is different than a voltage at the source terminal and a voltage at the drain terminal;
- and
- a second MOSFET having same type of charge carrier as the first MOSFET and configured in a stacked arrangement with the first MOSFET such that a reference voltage is generated at a node interconnecting the first MOSFET to the second MOSFET, where threshold voltage of the first MOSFET and threshold voltage of the second MOSFET are designed to be the same and a gate terminal of the second MOSFET is directly coupled to a drain terminal of the second MOSFET.
A voltage reference circuit, comprising:
- a first metal-oxide semiconductor field-effect transistor (MOSFET) having a source terminal, a drain terminal, a gate terminal and a body terminal, where the gate terminal of the first MOSFET is directly coupled to the source terminal of the first MOSFET;
- a second MOSFET having same type of charge carrier as the first MOSFET and configured in a stacked arrangement with the first MOSFET such that a reference voltage is generated at a node interconnecting the first MOSFET to the second MOSFET, wherein threshold voltage of the first MOSFET and threshold voltage of the second MOSFET are designed to be the same and a gate terminal of the second MOSFET is directly coupled to a drain terminal of the second MOSFET;
- and
- a bias circuit configured to bias the body terminal of the first MOSFET with a bias voltage that changes with temperature changes so that the reference voltage is temperature independent.
Dependencies are inferred from the claim text.