Linear voltage regulator for low-power digital circuit of chip

Abstract

The present invention relates to a linear voltage regulator for a low-power digital circuit of a chip, comprising a reference voltage varying with a threshold voltage, a buffer formed by amplifiers, and a compensation capacitor. The reference voltage is used as an input end of the buffer, an output voltage of the buffer, having a current driving capability, is kept consistent with the reference voltage, and the compensation capacitor is configured to decrease the fluctuation range of the output voltage when a current load varies. The reference voltage comprises two gate-source voltages of an MOS operating in a sub-threshold region, and the reference voltage Vref satisfies the following relation: Vref∝β(|VGS1|+VGS2); the reference voltage Vref flows through the output buffer formed by the amplifiers to supply a voltage to a digital circuit. By adopting a reference related to the threshold voltage of the MOS, the reference voltage will also vary with the changes in the process conditions and ambient temperature, so that an output of a linear voltage regulator can reflect such changes in the conditions, thereby reducing the operating supply voltage of the digital circuit and greatly reducing the power consumption accordingly.

Dependencies are inferred from the claim text.