Manufacture method of IPS TFT-LCD array substrate and IPS TFT-LCD array substrate

An in-plane switching thin film transistor liquid crystal display (IPS TFT-LCD) array substrate, comprising a substrate, a plurality of gate scan lines, a plurality of data lines, a plurality of common electrode lines and a plurality of pixel units, divided by the plurality of gate scan lines and the plurality of data lines which are mutually insulated and staggered, and aligned in an array;

• wherein each pixel unit comprises:
• a gate formed on the substrate, a gate isolation layer formed on the gate and the substrate, a semiconductor layer correspondingly above the gate and formed on the gate isolation layer, a source, a drain and a pixel electrode formed on the semiconductor layer and the gate isolation layer, an insulation protective layer formed on the source, the drain, the pixel electrode, the semiconductor layer and the gate isolation layer, and a common electrode formed on the insulation protective layer;
• the pixel electrode, the source, the drain and the data lines are obtained after patterning a source-drain metal layer, and the common electrode lines, the gate and the gate scan lines are obtained after patterning a gate metal layer;
• a via is provided in the insulation protective layer and the gate isolation layer correspondingly above the common electrode line, and the common electrode contacts with the common electrode line through the via;
• the source and the drain respectively contact with two ends of the semiconductor layer;
• wherein the common electrode is located above and isolated from the pixel electrode, the common electrode being spaced from the substrate by a distance greater than a distance by which the pixel electrode is spaced from the substrate.

A manufacture method of an in-plane switching thin film transistor liquid crystal display (IPS TFT-LCD) array substrate, comprising steps of:

• step 1, providing a substrate, and depositing a gate metal layer on the substrate, and patterning the gate metal layer to obtain a gate, a common electrode line and a gate scan line;
• step 2, depositing a gate isolation layer on the gate metal layer, and depositing an amorphous silicon layer on the gate isolation layer, and patterning the amorphous silicon layer after performing N-type doping to the amorphous silicon layer to obtain a semiconductor layer correspondingly above the gate;
• step 3, depositing a source-drain metal layer on the semiconductor layer and the gate isolation layer, and patterning the source-drain metal layer to obtain a source, a drain, a pixel electrode and a data line, and the source and the drain respectively contact with two ends of the semiconductor layer;
• step 4, depositing an insulation protective layer on the source-drain metal layer, and patterning the insulation protective layer and the gate isolation layer to form a via correspondingly above the common electrode line in the insulation protective layer and the gate isolation layer;
• step 5, depositing a transparent conductive layer on the insulation protective layer, and patterning the transparent conductive layer to obtain a common electrode, and the common electrode contacts with the common electrode line through the via;
• wherein forming the pixel electrode is carried out posterior to forming the common electrode such that the common electrode is located above and isolated from the pixel electrode, the common electrode being spaced from the substrate by a distance greater than a distance by which the pixel electrode is spaced from the substrate;
• wherein the gate metal layer is deposited by physical vapor deposition in the step 1, and a film thickness of the deposited gate metal layer is 3000-6000 Å, and material of the gate metal layer is a stack combination of one or more of molybdenum, titanium, aluminum and copper;
• the step of patterning the gate metal layer comprises photoresist coating, exposure, development, wet etching and photoresist stripping in order;
• wherein the gate isolation layer and the amorphous silicon layer are deposited by chemical vapor deposition in the step 2, and a film thickness of the deposited gate isolation layer is 2000-5000 Å, and a film thickness of the deposited amorphous silicon layer is 1500-3000 Å, and the gate isolation layer is a silicon nitride layer, and the step of patterning the amorphous silicon layer comprises photoresist coating, exposure, development, wet etching and photoresist stripping in order;
• wherein the source-drain metal layer is deposited by physical vapor deposition in the step 3, and a film thickness of the deposited gate metal layer is 3000-6000 Å, and material of the source-drain metal layer is a stack combination of one or more of molybdenum, titanium, aluminum and copper;
• the step of patterning the source-drain metal layer comprises photoresist coating, exposure, development, wet etching and photoresist stripping in order;
• wherein the insulation protective layer is deposited by chemical vapor deposition in the step 4, and a film thickness of the deposited insulation protective layer is 2000-5000 Å, and the insulation protective layer is a silicon nitride layer, and the step of patterning the insulation protective layer comprises photoresist coating, exposure, development, wet etching and photoresist stripping in order;
• wherein the transparent conductive layer is deposited by physical vapor deposition in the step 5, and a film thickness of the deposited transparent conductive layer is 400-1000 Å, and material of the transparent conductive layer is one or more of Indium Tin Oxide, Aluminum Tin Oxide, Aluminum Zinc Oxide, Indium Germanium Zinc Oxide;
• the step of patterning the transparent conductive layer comprises photoresist coating, exposure, development, wet etching and photoresist stripping in order.