US 10,310,013 B2 · Test mode isolation and power reduction in embedded core-based digital systems of integrated circuits (ICs) with multiple power domains

Abstract

Embodiments include a power isolation circuit. The power isolation circuit includes a logic block, a wrapper cell, an isolation cell, a test control unit, and/or a power control unit. The power control unit is coupled to the isolation cell and configured to receive a DFT internal core test mode control signal and a clamp control signal, and control the isolation cell dependent on the DFT internal core test mode control signal and the clamp control signal. Also disclosed is a multi-power domain multi-power isolation system, which includes a first power domain and a second power domain. The first power domain includes a logic block, wrapper cells, isolation cells, and a power control unit. The second power domain includes a logic block, wrapper cells, and level-shifter cells. The power control unit is coupled to the isolation cells. Additional power domains with similar characteristics can be included in the design.

Claims20

Dependent claims

An apparatus, comprising:

a logic block;
a wrapper cell coupled to the logic block;
an isolation cell coupled to the wrapper cell;
and
a power control unit coupled to the isolation cell and configured to receive a DFT internal core test mode control signal and a clamp control signal, and to control the isolation cell based, at least in part, upon the DFT internal core test mode control signal and the clamp control signal.

2 more elements

A multi-power domain multi-power isolation system, comprising:

a first power domain comprising a first logic block, a first plurality of wrapper cells coupled to the first logic block, a plurality of isolation cells, and a power control unit;
and
a second power domain comprising a second logic block, a second plurality of wrapper cells coupled to the second logic block, and a plurality of level-shifter cells,
wherein:
each isolation cell from among the plurality of isolation cells is coupled to a corresponding wrapper cell from among the first plurality of wrapper cells;
each level-shifter cell from among the plurality of level-shifter cells is coupled to a corresponding wrapper cell from among the second plurality of wrapper cells;
an output terminal of each isolation cell from among the plurality of isolation cells is coupled to an input terminal of each level-shifter cell from among the plurality of level-shifter cells;
and
the power control unit is coupled to the plurality of isolation cells in the first power domain.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application

15/470,880Filed 27 Mar 2017 · us provisional application

Priority

12 Dec 2016

Published

US 2018/0164376 A114 Jun 2018

Granted

4 Jun 2019

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

G01R 31/31721
Testing of digital circuits: power aspects, e.g. power supplies for test circuits, power saving during test
G01R 31/31701
Testing of digital circuits: arrangements for setting the Unit Under Test [UUT] in a test mode
G01R 31/318508
Test of Modular systems, e.g. Wafers, MCM's: board Level Test, e.g. P1500 Standard
G01R 31/31723
Testing of digital circuits: hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for…

Test mode isolation and power reduction in embedded core-based digital systems of integrated circuits (ICs) with multiple power domains

Life of this patent

Test mode isolation and power reduction in embedded core-based digital systems of integrated circuits (ICs) with multiple power domains

Life of this patent

Abstract

Claims20