Lightweight, low overhead debug bus

A method comprising:

• transmitting a debug command via an interconnect bus configured to connect to combinatorial logical blocks during normal operation of a processor and operate synchronous to a core clock;
• translating the debug command between the interconnect bus and a debug bus, wherein the debug bus comprises a plurality of debug wrapper circuits arranged in a daisy chain for unidirectional communication and that operate synchronous to the core clock;
• in response to the debug command, placing data from a selected debug wrapper circuit on the debug bus;
• and
• returning the data via the interconnect bus.

A system comprising:

• a graphic processing circuit configured to operate synchronous to a core clock, and manipulate and alter data in a memory to create images for output to a display device;
• an interconnect bus configured to connect to combinatorial logical blocks during normal operation of the graphic processing circuit and operate synchronous to the core clock;
• an interconnect-to-debug bus interface configured to translate communications between the interconnect bus and a debug bus;
• the debug bus comprising a plurality of debug wrapper circuits arranged in a daisy chain for unidirectional communication, and configured to operate synchronous to the core clock;
• and
• wherein each of the plurality of debug wrapper circuits is configured to:
• identify if the respective debug wrapper circuit is activated by the debug bus,
• receive a non-invasive input from a respective combinatorial logic block, and
• place the non-invasive input from the respective combinatorial logic block on the debug bus.