Master-slave clock generation circuit

A method, comprising:

• generating, by a first delay circuit of a clock generation circuit based on a clock signal, a slave clock signal and a delayed clock signal;
• generating, by a first tristate inverter of the clock generation circuit, at least a first portion of a master signal based on the clock signal and a scan enable signal;
• generating, by a second tristate inverter of the clock generation circuit, at least a second portion of the master signal based on the delayed clock signal and the scan enable signal;
• generating, by a second delay circuit of the clock generation circuit based on the generated portions of the master signal, a master clock signal;
• storing, by a master latch, a first value based on the master clock signal;
• and
• storing, by a slave latch, a second value based on the slave clock signal, wherein the second value is output by the master latch.

A non-transitory computer readable storage medium having stored thereon design information that specifies a circuit design in a format recognized by a fabrication system that is configured to use the design information to fabricate a hardware integrated circuit that includes:

• a master latch configured to store a first value based on a master clock signal and an inverted master clock signal;
• a slave latch configured to store a second value based on a slave clock signal and an inverted slave clock signal;
• a clock generation circuit, comprising:
• a first delay circuit configured to receive a clock signal and generate, based on the clock signal, the slave clock signal, the inverted slave clock signal, and a delayed clock signal;
• a first tristate inverter configured to generate at least a first portion of a master signal based on the clock signal and a scan enable signal;
• a second tristate inverter configured to generate at least a second portion of the master signal based on the delayed clock signal and the scan enable signal, wherein the output of the first tristate inverter is connected to the output of the second tristate inverter;
• and
• a second delay circuit configured to receive the master signal and generate, based on the generated portions of the master signal, the master clock signal and the inverted master clock signal.