Cell of transmission gate free circuit and integrated circuit and integrated circuit layout including the same

A semiconductor standard cell of a flip-flop circuit, the semiconductor standard cell comprising:

• a plurality of semiconductor fins extending substantially parallel to each other along a first direction;
• a plurality of electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction;
• and
• a plurality of gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level,
• wherein the semiconductor standard cell has a predetermined length in the first direction and a predetermined width in the second direction,
• the flip-flop circuit includes a plurality of transistors implementing at least an AND-OR-Invert (AOI) logic or an OR-AND-Invert (OAI) logic receiving an input data signal and an input clock signal, a storage block storing the input data signal, and an output block outputting a data output signal indicative of the stored data,
• the input clock signal is only either a clock signal or another clock signal complementary to the clock signal received by the semiconductor standard cell in an area defined by the predetermined length and the predetermined width, and
• the data input signal, the input clock signal, and the data output signal are transmitted among the plurality of transistors at least through the plurality of electrically conductive wirings.

An integrated circuit, comprising:

• a first semiconductor standard cell of a flip-flop circuit and a second semiconductor standard cell immediately adjacent to each other in a first direction,
• wherein the first semiconductor standard cell comprising:
• a plurality of semiconductor fins extending substantially parallel to each other along a first direction;
• a plurality of electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction;
• and
• a plurality of gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level,
• wherein the first semiconductor standard cell has a predetermined length in the first direction and a predetermined width in the second direction,
• the flip-flop circuit includes a plurality of transistors made of the plurality of semiconductor fins and the plurality of gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to an input clock signal,
• the input clock signal is only either a clock signal or another clock signal complementary to the clock signal received by the first semiconductor standard cell in an area defined by the predetermined length and the predetermined width, and
• the data input signal, the input clock signal, and the data output signal are transmitted among the plurality of transistors through at least the plurality of electrically conductive wirings, and
• the first semiconductor standard cell and the second semiconductor standard cell includes one or more dummy gate electrodes disposed on a boundary of the first semiconductor standard cell and the second semiconductor standard cell, and
• at least one of the one or more dummy gate electrodes extends continuously to cross the plurality of semiconductor fins.