US 10,256,274 B2 · Semiconductor memory device

Abstract

According to the embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first memory cell, a second memory cell, a third conductive layer, a first contact, a intermediate memory cell, a fourth conductive layer, a third memory cell, a fifth conductive layer, and a second contact. The third conductive layer is separated from the first conductive layer and the second conductive layer in a third direction crossing a first direction and crossing a second direction and extends in the second direction. The fifth conductive layer is separated from the second conductive layer in the third direction and extends in the second direction. A first length of the second conductive layer along the second direction is shorter than a second length of the fifth conductive layer along the second direction.

A memory device comprising:

a substrate;
a plurality of first wirings extending in a first direction, the plurality of first wirings being arranged in a second direction crossing the first direction;
a plurality of second wirings being provided between the substrate and the plurality of first wirings, the plurality of second wirings being adjacent to the plurality of first wirings in a third direction crossing the first and second direction and perpendicular to a surface of the substrate, the plurality of second wirings extending in the first direction, the plurality of second wirings being arranged in the second direction;
a plurality of third wirings being provided between the plurality of first wirings and the second wirings in the third direction, the plurality of third wirings extending in the second direction and being arranged in the first direction;
a plurality of first resistance changeable layers being provided between the plurality of first wirings and the plurality of third wirings;
a plurality of second resistance changeable layers being provided between the plurality of second wirings and the plurality of third wirings;
a first memory cell array being comprised of the plurality of the first resistance changeable layers and the plurality of second resistance changeable layers;
a plurality of fourth wirings being provided between the substrate and the plurality of first wirings, the plurality of fourth wirings being adjacent to the plurality of first wirings in the third direction, the plurality of fourth wirings extending in the first direction and being arranged in the second direction, the plurality of fourth wirings being adjacent to the plurality of second wirings in the first direction;
a plurality of the fifth wirings being provided between the plurality of first wirings and the plurality of fourth wirings in the third direction, the plurality of fifth wirings extending in the second direction and being arranged in the first direction;
a plurality of third resistance changeable layers being provided between the plurality of first wirings and the plurality of fifth wirings;
a plurality of fourth resistance changeable layers being provided between the plurality of fourth wirings and the plurality of fifth wirings;
a second memory cell array being comprised of the plurality of third resistance changeable layers and the plurality of fourth resistance changeable layers;
a first contact electrically connected to the first wiring, being provided between the first memory cell array and the second memory cell array in the first direction, and extending in the third direction;
a second contact electrically connected to the second wiring, the second contact being shorter than the first contact in the third direction, and extending in the third direction;
a third contact electrically connected to the third wiring, the third contact being shorter than the first contact in the third direction, and extending in the third direction;
a first circuit element electrically connected to the second contact;
and
a second circuit element electrically connected to the third contact.

15 more elements

Semiconductor memory device

Life of this patent

Semiconductor memory device

Life of this patent

Abstract

Claims18